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DRV8350F: DRV8350F - MOSFET placement

Sebastian Siegfried
Intellectual 680 points
Part Number: DRV8350F

Hi,

I have a previous design with SO-08 MOSFETs and want now to use D2PAK for better thermal resistance and also to have the decoupling caps near the FETs and still be able to use a coolant. Now I'm unsure about the placement of the MOSFETs and the path to the Gates are way larger than for SO-08 packages. Is there any problem in my placement of the motor driver and the MOSFETs? I think I minimized the parasitic inductances as way as possible, the only thing I could do is to have the DRV8350F on top of the FETs, but this will probably not really reduce the inductance, especially since vias are needed.

Kind Regards,

Sebastian

  • 0
    TI__Mastermind 26046 points

    Hi Sebastian, 

    Thanks for your inquiry, glad you're aware of parasitic inductances and potential effects on gate driver and MOSFET performance. 

    It is okay to place the FETs on opposite layer of the DRV device as long as there's one via in the gate drive path. As a general rule of thumb, whenever parasitic inductance occurs due to vias, thin traces, or long traces, always try to mitigate parasitics with thick, wide, and shorter traces wherever possible. This includes:

    - 15-20 mil wide traces for gate drive outputs (GHx, SHx, GLx, SLx)
    - Wide copper pours for high current motor paths (we recommend 10mil/A, and use multiple layers if possible with plenty of direct connect vias to lessen inductance. Check out the DRV8350x-EVM layout for suggestions. 

    Just ensure that whichever side the DRV8350F is on, place regulator caps as close as possible to the DRV device to minimize inductance in current loops (VM, VDRAIN, VCP, VGLS, CPH-CPL, etc.)

    Please check out these resources for layout suggestions:

    - https://www.ti.com/lit/pdf/slva959

    - https://www.ti.com/lit/pdf/slvaf66

    Thanks,
    Aaron