DRV8353: DRV8353

Hi Leo! 

Thank you for reaching out on our forum. 

I would be happy to help with a schematic review - can you please upload here the DRV8353 schematic in PDF form? 

Best Regards,

-Joshua

See attached. Please focus on p1 and 4 where the totem pole and DRV8353 are.
We had many failures in our current design with phase current of ~ 300A. Likely caused by the external voltage spike across SP and SN.

TI_Review.pdf

I am also considering bypass the low-side current amplifier of the DRV and replace them with INA series. Are you able to recommend a part that supports 54V nominal application with 300A of transient current measurement?

Thanks Leo! 

I will look into the schematic information, so please look forward to the feedback by the end of Wednesday.  

Regarding the CSA selection I am not currently familiar,  and may recommend actually posting another E2E to receive guidance from the Instrumentation Amplifier product line engineers.

Best Regards,

-Joshua

Thank you!
My biggest worry is the integrated current sense opamp failing after reading a bunch of posts on TI's E2E.
Please note the abs max operating condition is 300A phase current for 2sec. I had parallel CSR (WSHP28181L000FEA) to support the pulse "overload" but I really want to make sure the RC element connected to the internal op-amp is properly tuned.

Hi Leo, 

Of course! I understand the concern, however as long as the shunt resistor is sufficiently sized to reduce the voltage observed on the CSA input pins, there should be no issue as long as this high worst-case scenario is kept in mind during the design phase. 

I am still overviewing the design but will follow-up within a day with my additional feedback.

Best Regards,

-Joshua

Correct, however, my worry is mostly Ldi/dt stuff not V=IR. Can you recommend anyone to recommend an INA part that can be sensing the same phase current in addition to the DRV?

Joshua,

Do you foresee DRV8353 have trouble enabling paralleled IPTC012N08NM5ATMA1 FETs for 20kHz switching frequency?

Total Qg=440 nC @ 10 V.

Can you also share the ds of DRV3255-Q1 ? Please send me a NDA.

Hi Leo, 

Thank you for the clarification and additional questions here.  

Let me see if there may be a good INA recommendation for your application. 

For the parallel FETs i would recommend MOSFETs with a much lower Qgd (>100nC).

For the datasheet and NDA request,  please reach out over email or through another E2E thread with that request as the topic, since I am unable to provide that.  

Best Regards, 

-Joshua

My intent is to have symmetric RC filter applied to the CSA, however, DRV8353 does not differentiate between SPx and LS FET source connection thus R202 = 0ohm (ideally it should be 5 ohm).

I will probably make R202=5ohm and reduce LS gate resistor = 0 ohm.

Do you have a set of recommended values for IAUS300N10S5N015TATMA1 MOSFET?

This is our current setting.
Fsw: 20kHz
1% DT= 1/(20e3)/100/1e-6= 500nS

SPI reg setting
tDEAD=11b (500ns DT i.e. 1% of Fsw)
I_DRIVEP (mid pull up)
I_DRIVEP_HS or I_DRIVEP_LS=1000b (550mA)

I_DRIVEN
I_DRIVEN_HS=100b (1000mA) moderate pull down when LS turn on
I_DRIVEN_LS= 111b (2000mA) strong pull down when HS turn on

tDRIVE= 11b default setting. No change.

Josh,

Another question for you.
Can you help confirm the following calculation is correct for "single supply power dissipation" as mentioned in DRV8353 ds eqn 33-38 ?
Do you know why the ds assumes 3 FETs are switching at any given time (see attached)?

We run FOC + SVPWM modulation so 1 FET changes state from one vector to the next, nominally.
Calculation leads to Tj ~ 130C (150C as abs max).

See blow

FET_num=2;
Qg=226e-9; %IPTC012N08NM5ATMA1/IPTC011N08NM5ATMA1
Qg_tot=FET_num*Qg
Fsw=20e3;
Vbus=58;
I=FET_num*Qg*Fsw*1

Pvcp=I*(Vbus*2)*2 % 2 HS ON
Pvgls=I*(Vbus)*1 % 1 LS ON
Ptot=Pvcp+Pvgls
Tj=60+26.6*Ptot

In addition.

FET_num=2;
Qg=223; %IPTC012N08NM5ATMA1/IPTC011N08NM5ATMA1
Qg_tot=FET_num*Qg
Fsw=20e3;
Factor=1/100;
rise_time_ns=Factor*(1/Fsw)/1e-9
I=Qg_tot/rise_time_ns

With Idrive <1A the DRV8353 should be able to support 2 paralleled FETs.
Let me know if this is correct. 

Joshua,

RE: "And I believe the DS is grouping the high side and lowsides together per entire commutation cycle,"

I'm not sure if I'd agree to the calculation even its per commutation cycle basis. 

There are only 3 FETs on at any given vector of SVPWM i.e. the "x3" in eqn(33) is incorrect (unless the gate driver is consuming the same amount of current even when the FET is off).

Regardless of which vector the controller stays in there are 3 FETs that are not consuming gate driver current.

Is my understanding correct?

Hi Leo, 

Please let me look into this a bit further over the Thanksgiving holiday to better explain this topic and follow-up at the start of next with further response. 

 Best Regards,

-Joshua

Josh,

Can you please provide an update to this topic? Thx!