BOOSTXL-DRV8305EVM: 3PWM mode

Vibhav Kulkarni

Tool/software:

Hello Team,
We are interfacing LAUNCHXL F28379D and BOOSTXL-DRV8305EVM.
We used command (0x3896) to write at 0x7 for configuring DRV for 3PWM mode.
For confirming this configuration we read back this address and got 0x0096 on SPI.

Now...
In 3PWM mode, DRV8305EVM generates complimentary low-side signals internally.
But when when we gave ePWM signal on GPIO0(EPWM1A) of LAUNCHXL F28379D, we didn't get any complimentary ePWM signal onGPIO1(EPWM1A).

Doubt :- Is the value written at 0x7 really configured.

Please tell if we are missing any other steps to get DRV working.

3 months ago

0 Vibhav Kulkarni 3 months ago

Prodigy 50 points

Hello Team ,

My test case is to configure ePWM1 just for channel EPWM1A(GPIO0), connect with DRV8305EVM and observe complimentary PWM signal being generated on EPWM1B(GPIO1).

Problem I am facing is that I don't observe any complimentary waveform on EPWM1B(GPIO1)

Here is my code

//
// Included Files
//
#include "F28x_Project.h"
#include "driverlib.h"
#include "device.h"

#define PWM_PERIOD 1250    // Define the period for PWM
#define ADC_MAX 4095.0     // Assuming 12-bit ADC (0 to 4095)

uint16_t txData = 0x3896;
volatile uint16_t rxData;
volatile uint16_t rxData1;
volatile uint16_t rxData2;

void InitEPwm1(void);
void InitEPwm1gpio(void);

void Init_DRV8305_EN_GATE_WAKE(void);    // Wake and enable driver
void InitSPIAGPIO(void);                 // SPIA GPIO + unlock + CPU1 select
void InitSPIA(void);                     // SPIA peripheral

void dummy(void); // Used in debugging (to confirm that We are not getting corrupt data) 




// =======================
// MAIN FUNCTION
// =======================
void main(void)
{
    // Step 1: Initialize System
    InitSysCtrl();

    //Step2: GPIO configuration
    

    InitEPwm1();
    InitEPwm1gpio();
    Init_DRV8305_EN_GATE_WAKE();    // Wake and enable driver
    InitSPIAGPIO();                 // SPIA GPIO + unlock + CPU1 select
    InitSPIA();                     // SPIA peripheral
    DELAY_US(2000);                 // Wait for DRV8305 ready
    
    while (1)
    {
         // Send data
        SPI_writeDataBlockingNonFIFO(SPIA_BASE, txData);
        // Read received data
        rxData = SPI_readDataBlockingNonFIFO(SPIA_BASE);


         // Send data
        SPI_writeDataBlockingNonFIFO(SPIA_BASE, 0xB800);
        // Read received data
        rxData1 = SPI_readDataBlockingNonFIFO(SPIA_BASE); 

         if(rxData1 != 0x0096)
        {
            dummy();
        }

    }
}

// =======================
// Initialize ePWM1
// =======================

void InitEPwm1(void)
{
    EALLOW;
    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    EDIS;

    EPwm1Regs.TBCTL.bit.CTRMODE = 2;  // Up-Down count mode for center-aligned PWM
    EPwm1Regs.TBPRD = PWM_PERIOD;     // Set period
    EPwm1Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Divider value for ePWM clock divides by .. /1
    EPwm1Regs.TBCTL.bit.CLKDIV = 0; // Divider value for ePWM clock divides by .. /1

    EPwm1Regs.CMPA.bit.CMPA = PWM_PERIOD / 4; // Initial duty cycle 50%
    
    //EPWM1A
    EPwm1Regs.AQCTLA.bit.CAU = 2;  // Set PWM1A on counter up
    EPwm1Regs.AQCTLA.bit.CAD = 1;  // Clear PWM1A on counter down

    // EPWM1B:(complement of A)
    // EPwm1Regs.AQCTLB.bit.CAU = 1;  // Clear
    // EPwm1Regs.AQCTLB.bit.CAD = 2;  // Set
}

// =======================
// Initialize ePWM1
// =======================

void InitEPwm1gpio(void)
{
    EALLOW;
    //  GPIO0 configuration for  Output ePWM1A
    GpioCtrlRegs.GPALOCK.bit.GPIO0 = 0; //Unlock GPIO configuration registers for PORT C
    GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM1A (O)
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM1A (O)
    GpioCtrlRegs.GPACSEL1.bit.GPIO0 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit.GPIO0 = 1 ; // Set GPIO 0 Direction AS OUTPUT

    //  GPIO1 configuration for  Output ePWM1B
    GpioCtrlRegs.GPALOCK.bit.GPIO1 = 0; //Unlock GPIO configuration registers for PORT C
    GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM1A (O)
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM1A (O)
    GpioCtrlRegs.GPACSEL1.bit.GPIO1 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit.GPIO1 = 1 ; // Set GPIO 0 Direction AS OUTPUT

     EDIS;
}


// =======================
// ENABLE DRV8305 VIA GPIO
// =======================

void Init_DRV8305_EN_GATE_WAKE()
{
    EALLOW;

    // GPIO124 (EN_GATE)
    GpioCtrlRegs.GPDLOCK.bit.GPIO124 = 0; // Unlock config
    GpioCtrlRegs.GPDCSEL4.bit.GPIO124 = 0; // CPU1 owns pin

    GpioCtrlRegs.GPDGMUX2.bit.GPIO124 = 0;
    GpioCtrlRegs.GPDMUX2.bit.GPIO124 = 0;
    GpioCtrlRegs.GPDDIR.bit.GPIO124  = 1;
    GpioDataRegs.GPDSET.bit.GPIO124  = 1;

    //  GPIO125 (WAKE)
    GpioCtrlRegs.GPDLOCK.bit.GPIO125 = 0; // Unlock config
    GpioCtrlRegs.GPDCSEL4.bit.GPIO125 = 0; // CPU1 owns pin

    GpioCtrlRegs.GPDGMUX2.bit.GPIO125 = 0;
    GpioCtrlRegs.GPDMUX2.bit.GPIO125 = 0;
    GpioCtrlRegs.GPDDIR.bit.GPIO125  = 1;
    GpioDataRegs.GPDSET.bit.GPIO125  = 1;

    EDIS;

    DEVICE_DELAY_US(30000); // SPI input data hold time delay
}

// =======================
// SPIA GPIO CONFIGURATION
// =======================
void InitSPIAGPIO()
{
    EALLOW;

    // Unlock and assign ownership to CPU1 for GPIO58–61
    GpioCtrlRegs.GPBLOCK.bit.GPIO58 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO58 = 0; //CPU1 MASTER CORE

    GpioCtrlRegs.GPBLOCK.bit.GPIO59 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO59 = 0; //CPU1 MASTER CORE
 
    GpioCtrlRegs.GPBLOCK.bit.GPIO60 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO60 = 0; //CPU1 MASTER CORE

    GpioCtrlRegs.GPBLOCK.bit.GPIO61 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO61 = 0; //CPU1 MASTER CORE

    // Configure MUX and GMUX for SPIA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // SPISIMO-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO58  = 3;

    GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 3; // SPISOMI-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO59  = 3;

    GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // SPICLK-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO60  = 3;

    GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 3; // SPISTE-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO61  = 3;

    // Async qualification
   // GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;
    GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;
   // GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;
   // GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;

    // Direction
    GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // output
    GpioCtrlRegs.GPBDIR.bit.GPIO59 = 0; // input
    GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1; // output
    GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // output

    GpioDataRegs.GPBSET.bit.GPIO61 = 1; // output

    EDIS;
}

// =======================
// SPIA MODULE SETUP
// =======================
void InitSPIA()
{
    EALLOW;
    CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;

    SpiaRegs.SPICCR.all = 0x000F;              // 16-bit char
    SpiaRegs.SPICTL.all = 0x0007;              // Master mode, clock phase = 1
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;   //clock polarity = 0
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 49;     // 1 MHz SPI

    SpiaRegs.SPICCR.bit.SPISWRESET = 1;
    SpiaRegs.SPIPRI.bit.FREE = 1;
    EDIS;
}

// Used in debugging (to confirm that We are not getting corrupt data) 
void dummy (void)
{
    
}

//
// End of File
//

0 Vibhav Kulkarni 3 months ago in reply to Vibhav Kulkarni

Prodigy 50 points

Hey team,
we got complimentary ePWM signal when we probed on the MOSFET terminal (MOSFET - Q4 , pin 4).
But we observe shoot through in the waveforms between EPWM1A and EPWM1B (when EPWM1 is going high).

waiting for response from the team.........

0 Yara Al Shami 3 months ago in reply to Vibhav Kulkarni

TI__Genius 15335 points

Hi Vibhav,

I'm not sure where your issue is stemming from, is the PWM output from the MCU the desired output? When you say shoot through do mean on the driver's outputs?

Regards,

Yara

0 Vibhav Kulkarni 3 months ago in reply to Yara Al Shami

Prodigy 50 points

It is clearly mentioned in TI LAUNCHXL F28379D reference manual that the complimentary low side signals are generated internally and Deadtime can be adjusted through the internal setting (DEAD_TIME) in the SPI registers.

this confirms that shoot through is introduced from driver side

so when we write 0x3896, we are configuring these two fields remaining fields at this address are default.
1) PWM_MODE = b'01 (for PWM with 3 independent inputs) at address 0x7.
2) COMM_OPTION = b'0 (for diode freewheeling )
remaining fields at this address are default. (DEAD_TIME = 52ns which is default)

with this configuration, shoot through is seen between EPWM1A and EPWM1B (when EPWM1 is going high) in the waveforms shown below.

0 Vibhav Kulkarni 3 months ago in reply to Vibhav Kulkarni

Prodigy 50 points

Please tell if I am missing any configurations in other the control registers.

0 Vibhav Kulkarni 3 months ago in reply to Vibhav Kulkarni

Prodigy 50 points

Hello,
When I configure DRV8305EVM for 3PWM mode, I am expecting these waveforms to appear as marked in the snippet. Is my expectation right ?
Why is DRV8305EVM not producing these waveforms when the DEAD_TIME is configured ??
I am probing (GL_A, GL_B, GL_C) where complimentary low side signals are generated internally by the DRV8305EVM

Attaching the updated source code for configuring DRV8305EVM in (PWM with 3 independent inputs) mode

//
// Included Files
//
#include "F28x_Project.h"
#include "driverlib.h"
#include "device.h"

#define PWM_PERIOD 1250    // Define the period for PWM


uint16_t txData = 0x3A95;
volatile uint16_t rxData;
volatile uint16_t rxData1;
volatile uint16_t rxData2;

void InitEPwm1(void);
void InitEPwm1gpio(void);

void InitEPwm2(void);
void InitEPwm2gpio(void);

void InitEPwm3(void);
void InitEPwm3gpio(void);

void Init_DRV8305_EN_GATE_WAKE(void);    // Wake and enable driver
void InitSPIAGPIO(void);                 // SPIA GPIO + unlock + CPU1 select
void InitSPIA(void);                     // SPIA peripheral

void dummy(void); // Used in debugging (to confirm that We are not getting corrupt data) 




// =======================
// MAIN FUNCTION
// =======================
void main(void)
{
    // Step 1: Initialize System
    InitSysCtrl();

    //Step2: GPIO configuration

    Init_DRV8305_EN_GATE_WAKE();    // Wake and enable driver
    InitSPIAGPIO();                 // SPIA GPIO + unlock + CPU1 select
    InitSPIA();                     // SPIA peripheral
    DELAY_US(2000);                 // Wait for DRV8305 ready    

    InitEPwm1();
    InitEPwm1gpio();
    InitEPwm2();
    InitEPwm2gpio();
    InitEPwm3();
    InitEPwm3gpio();

    while (1)
    {
        // Send data ON 0X7 FOR 3PWM MODE SELECTION AND DEADBAN CONFIGURATION 
        SPI_writeDataBlockingNonFIFO(SPIA_BASE, txData);
        // Read received data
        rxData = SPI_readDataBlockingNonFIFO(SPIA_BASE);
        
        SPI_writeDataBlockingNonFIFO(SPIA_BASE, 0x8800);
        // Read received data
        rxData = SPI_readDataBlockingNonFIFO(SPIA_BASE);
        
        SPI_writeDataBlockingNonFIFO(SPIA_BASE, 0x9000);
        // Read received data
        rxData = SPI_readDataBlockingNonFIFO(SPIA_BASE);
        
        
        SPI_writeDataBlockingNonFIFO(SPIA_BASE, 0x9800);
        // Read received data
        rxData = SPI_readDataBlockingNonFIFO(SPIA_BASE);

        SPI_writeDataBlockingNonFIFO(SPIA_BASE, 0xA000);
        // Read received data
        rxData = SPI_readDataBlockingNonFIFO(SPIA_BASE);
        
        // Send data
        // SPI_writeDataBlockingNonFIFO(SPIA_BASE, 0xB800);
        // // Read received data
        // rxData1 = SPI_readDataBlockingNonFIFO(SPIA_BASE); 

         if(rxData1 != 0x0096)
        {
            dummy();
        }

    }
}

// =======================
// Initialize ePWM1
// =======================

void InitEPwm1(void)
{
    EALLOW;
    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    EDIS;

    EPwm1Regs.TBCTL.bit.CTRMODE = 2;  // Up-Down count mode for center-aligned PWM
    EPwm1Regs.TBPRD = PWM_PERIOD;     // Set period
    EPwm1Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Divider value for ePWM clock divides by .. /1
    EPwm1Regs.TBCTL.bit.CLKDIV = 0; // Divider value for ePWM clock divides by .. /1

    EPwm1Regs.CMPA.bit.CMPA = PWM_PERIOD / 2; // Initial duty cycle 50%
    
    //EPWM1A
    EPwm1Regs.AQCTLA.bit.CAU = 2;  // Set PWM1A on counter up
    EPwm1Regs.AQCTLA.bit.CAD = 1;  // Clear PWM1A on counter down

    // EPWM1B:(complement of A)
    // EPwm1Regs.AQCTLB.bit.CAU = 1;  // Clear
    // EPwm1Regs.AQCTLB.bit.CAD = 2;  // Set
}

// =======================
// Initialize ePWM1 GPIO
// =======================

void InitEPwm1gpio(void)
{
    EALLOW;
    //  GPIO0 configuration for  Output ePWM1A
    GpioCtrlRegs.GPALOCK.bit.GPIO0 = 0; //Unlock GPIO configuration registers for PORT A
    GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM1A (O)
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM1A (O)
    GpioCtrlRegs.GPACSEL1.bit.GPIO0 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit.GPIO0 = 1 ; // Set GPIO 0 Direction AS OUTPUT

    //  GPIO1 configuration for  Output ePWM1B
    // GpioCtrlRegs.GPALOCK.bit.GPIO1 = 0; //Unlock GPIO configuration registers for PORT A
    // GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM1B (O)
    // GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM1B (O)
    // GpioCtrlRegs.GPACSEL1.bit.GPIO1 = 0 ;// Select CPU1 as MASTER CORE
    // GpioCtrlRegs.GPADIR.bit.GPIO1 = 1 ; // Set GPIO 0 Direction AS OUTPUT

     EDIS;
}


// =======================
// Initialize ePWM2
// =======================

void InitEPwm2(void)
{
    EALLOW;
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
    EDIS;

    EPwm2Regs.TBCTL.bit.CTRMODE = 2;  // Up-Down count mode for center-aligned PWM
    EPwm2Regs.TBPRD = PWM_PERIOD;     // Set period
    EPwm2Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // Divider value for ePWM clock divides by .. /1
    EPwm2Regs.TBCTL.bit.CLKDIV = 0; // Divider value for ePWM clock divides by .. /1

    EPwm2Regs.CMPA.bit.CMPA = PWM_PERIOD / 2; // Initial duty cycle 50%
    
    //EPWM1A
    EPwm2Regs.AQCTLA.bit.CAU = 2;  // Set PWM1A on counter up
    EPwm2Regs.AQCTLA.bit.CAD = 1;  // Clear PWM1A on counter down

    // EPWM1B:(complement of A)
    // EPwm1Regs.AQCTLB.bit.CAU = 1;  // Clear
    // EPwm1Regs.AQCTLB.bit.CAD = 2;  // Set
}

// =======================
// Initialize ePWM2 GPIO
// =======================

void InitEPwm2gpio(void)
{
    EALLOW;
    //  GPIO2 configuration for  Output ePWM2A
    GpioCtrlRegs.GPALOCK.bit.GPIO2 = 0; //Unlock GPIO configuration registers for PORT A
    GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM2A (O)
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM2A (O)
    GpioCtrlRegs.GPACSEL1.bit.GPIO2 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1 ; // Set GPIO 0 Direction AS OUTPUT

    //  GPIO3 configuration for  Output ePWM2B
    GpioCtrlRegs.GPALOCK.bit.GPIO3 = 0; //Unlock GPIO configuration registers for PORT A
    GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM2B (O)
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM2B (O)
    GpioCtrlRegs.GPACSEL1.bit.GPIO3 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit.GPIO3 = 1 ; // Set GPIO 0 Direction AS OUTPUT

     EDIS;
}

// =======================
// Initialize ePWM3
// =======================

void InitEPwm3(void)
{
    EALLOW;
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
    EDIS;

    EPwm3Regs.TBCTL.bit.CTRMODE = 2;  // Up-Down count mode for center-aligned PWM
    EPwm3Regs.TBPRD = PWM_PERIOD;     // Set period
    EPwm3Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // Divider value for ePWM clock divides by .. /1
    EPwm3Regs.TBCTL.bit.CLKDIV = 0; // Divider value for ePWM clock divides by .. /1

    EPwm3Regs.CMPA.bit.CMPA = PWM_PERIOD / 2; // Initial duty cycle 50%
    
    //EPWM1A
    EPwm3Regs.AQCTLA.bit.CAU = 2;  // Set PWM1A on counter up
    EPwm3Regs.AQCTLA.bit.CAD = 1;  // Clear PWM1A on counter down

    // EPWM1B:(complement of A)
    // EPwm1Regs.AQCTLB.bit.CAU = 1;  // Clear
    // EPwm1Regs.AQCTLB.bit.CAD = 2;  // Set
}

// =======================
// Initialize ePWM3 GPIO
// =======================

void InitEPwm3gpio(void)
{
    EALLOW;
    //  GPIO0 configuration for  Output ePWM3A
    GpioCtrlRegs.GPALOCK.bit. GPIO4 = 0; //Unlock GPIO configuration registers for PORT A
    GpioCtrlRegs.GPAGMUX1.bit. GPIO4 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM3A (O)
    GpioCtrlRegs.GPAMUX1.bit. GPIO4 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM3A (O)
    GpioCtrlRegs.GPACSEL1.bit. GPIO4 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit. GPIO4 = 1 ; // Set GPIO 0 Direction AS OUTPUT

    //  GPIO1 configuration for  Output ePWM3B
    GpioCtrlRegs.GPALOCK.bit. GPIO5 = 0; //Unlock GPIO configuration registers for PORT A
    GpioCtrlRegs.GPAGMUX1.bit. GPIO5 = 0 ; // GPIOC MUX for making pin 0 to function as EPWM3B (O)
    GpioCtrlRegs.GPAMUX1.bit. GPIO5 = 1 ; // GPIOC MUX for making pin 0 to function as EPWM3B (O)
    GpioCtrlRegs.GPACSEL1.bit. GPIO5 = 0 ;// Select CPU1 as MASTER CORE
    GpioCtrlRegs.GPADIR.bit. GPIO5 = 1 ; // Set GPIO 0 Direction AS OUTPUT

     EDIS;
}


// =======================
// ENABLE DRV8305 VIA GPIO
// =======================

void Init_DRV8305_EN_GATE_WAKE()
{
    EALLOW;

    // GPIO124 (EN_GATE)
    GpioCtrlRegs.GPDLOCK.bit.GPIO124 = 0; // Unlock config
    GpioCtrlRegs.GPDCSEL4.bit.GPIO124 = 0; // CPU1 owns pin

    GpioCtrlRegs.GPDGMUX2.bit.GPIO124 = 0;
    GpioCtrlRegs.GPDMUX2.bit.GPIO124 = 0;
    GpioCtrlRegs.GPDDIR.bit.GPIO124  = 1;
    GpioDataRegs.GPDSET.bit.GPIO124  = 1;

    //  GPIO125 (WAKE)
    GpioCtrlRegs.GPDLOCK.bit.GPIO125 = 0; // Unlock config
    GpioCtrlRegs.GPDCSEL4.bit.GPIO125 = 0; // CPU1 owns pin

    GpioCtrlRegs.GPDGMUX2.bit.GPIO125 = 0;
    GpioCtrlRegs.GPDMUX2.bit.GPIO125 = 0;
    GpioCtrlRegs.GPDDIR.bit.GPIO125  = 1;
    GpioDataRegs.GPDSET.bit.GPIO125  = 1;

    EDIS;

    DEVICE_DELAY_US(30000); // SPI input data hold time delay
}

// =======================
// SPIA GPIO CONFIGURATION
// =======================
void InitSPIAGPIO()
{
    EALLOW;

    // Unlock and assign ownership to CPU1 for GPIO58–61
    GpioCtrlRegs.GPBLOCK.bit.GPIO58 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO58 = 0; //CPU1 MASTER CORE

    GpioCtrlRegs.GPBLOCK.bit.GPIO59 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO59 = 0; //CPU1 MASTER CORE
 
    GpioCtrlRegs.GPBLOCK.bit.GPIO60 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO60 = 0; //CPU1 MASTER CORE

    GpioCtrlRegs.GPBLOCK.bit.GPIO61 = 0;
    GpioCtrlRegs.GPBCSEL4.bit.GPIO61 = 0; //CPU1 MASTER CORE

    // Configure MUX and GMUX for SPIA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // SPISIMO-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO58  = 3;

    GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 3; // SPISOMI-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO59  = 3;

    GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // SPICLK-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO60  = 3;

    GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 3; // SPISTE-A
    GpioCtrlRegs.GPBMUX2.bit.GPIO61  = 3;

    // Async qualification
   // GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;
    GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3;
   // GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3;
   // GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3;

    // Direction
    GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // output
    GpioCtrlRegs.GPBDIR.bit.GPIO59 = 0; // input
    GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1; // output
    GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // output

    GpioDataRegs.GPBSET.bit.GPIO61 = 1; // output

    EDIS;
}

// =======================
// SPIA MODULE SETUP
// =======================
void InitSPIA()
{
    EALLOW;
    CpuSysRegs.PCLKCR8.bit.SPI_A = 1;
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;

    SpiaRegs.SPICCR.all = 0x000F;              // 16-bit char
    SpiaRegs.SPICTL.all = 0x0007;              // Master mode, clock phase = 1
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;   //clock polarity = 0
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 49;     // 1 MHz SPI

    SpiaRegs.SPICCR.bit.SPISWRESET = 1;
    SpiaRegs.SPIPRI.bit.FREE = 1;
    EDIS;
}

// Used in debugging (to confirm that We are not getting corrupt data) 
void dummy (void)
{
    
}

//
// End of File
//

0 Yara Al Shami 3 months ago in reply to Vibhav Kulkarni

TI__Genius 15335 points

Hi Vibhav,

I'm not understanding completely when you say

Vibhav Kulkarni said:
with this configuration, shoot through is seen between EPWM1A and EPWM1B (when EPWM1 is going high) in the waveforms shown below.

can you tell me what EPWM1A,B, and 1 are? These are signals coming from the MCU correct? Do you have waveforms for the output of the device? That would tell us whether shoot through events are present or not.

It seems like these issues are stemming from the MCU and not the driver itself. Have you had a chance to look at the firmware linked in this E2E:

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1102004/drv8305-spi-interface

Regards,

Yara

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BOOSTXL-DRV8305EVM: 3PWM mode