This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Our customer have LED on PVDD line.
Even when they powered off PVDD, LED kept turning ON.
There seems to have leak current.
I have 2 questions.
[Question 1]
Is this because there is ESD protection diode between PVDD/GVDD and VDD ?
[Question 2]
The datasheet says there is no requirement for power sequence, but don't you need to power up PVDD first ?
Best Regards,
Kawai
Hi Kawai,
How long does the LED continue to be on after PVDD is powered off? There is usually a large capacitor on the PVDD line that must be discharged before the LED will turn off.
Please watch the voltage at PVDD after power is removed. If the voltage drops to a non-zero value and remains there, can you provide the schematic?
As stated in the datasheet, there is no requirement for the power sequence.
Thanks.
Hi Rick-san,
Thank you for your comments.
The LED is ON as long as 12V is powered to VDD and GVDD.
They observes 9V DC at PVDD when PVDD pin is not powered.
As we do not have DRV8332EVM, we tested with DRV8312EVM (Lower current version of DRV8332).
(Used external 12VDC power supply to VDD/GVDD, J1 connected to external 12V, No power to PVDD)
We observed 4.0VDC at PVDD line.
There seems to have leak from GVDD/VDD to PVDD.
Best Regards,
Kawai
Hi Kawai-san,
Thank you for the additional information. I will attempt to duplicate this in our lab.
It may be a few days before I have a response.
Hi Kawai-san,
I attempted to duplicate the customer finding but had no success. This was using an earlier version of the EVM (Rev B). The C2000 card was removed during the attempt to duplicate the finding. This was done to eliminate any potential effects of firmware.
We will attempt again once the latest version of the EVM arrives.
While waiting, please have the customer try the following:
1) Please remove the C2000 card when powering up GVDD/VDD only.
2) If the LED is still on, please examine the OUT_x signals. If any are above 0V, please locate the cause of this. Voltage on the OUT_x signals can pass through the diode of the high side FET to power PVDD.
3) Can you describe the motor connections, MOx? Is a motor or something else connected to the MOx pins?
Thank you.
Hi Kawai-san,
I was able to duplicate the finding. Here is what I have found to date. Again the C2000 card was removed to minimize variables.
As the GVDD/VDD is powered up the voltage on OUTA, OUTB, and OUTC began to rise. At 12V, each output had approximately 4.3V. At 4.3V current can flow through the high side body diodes to PVDD, which was about 3.9V.
I measured the voltage across R2 to determine how much current was flowing through the diode. It was 2.2V/4.99k or approximately 400uA.
Next I grounded the three outputs since they were not actively driven. On the power supply, I saw a 1mA rise in current. The PVDD LED turned off when I did this.
At this point, it appears to be some type of leakage but requires further debug to find it.
Hi Rick-san,
Thank you for confirming on your board.
Our customer is evaluating based on their original board.
I am asking the voltage at OUTx pins. Currently, they see 9V at PVDD pin.
Best Regards,
Kawai
Hi Rick-san,
Our customer observed around 10V at OUTx pins.
The leak voltage seems to be coming from the OUTx pins.
[Test Condition]
- VDD/GVDD=12V
- PWM_x pin = Low
- /RESET_x pin = Low / High (* Voltage observed on either setting.)
- 3 phase motor : connected / disconnected (* Voltage observed with either setting)
[Question 1]
Is this the correct operation for DRV8332 to output some kind of voltage on OUTx pin, when powering VDD and/or GVDD ?
The leak voltage on OUTx pin were observed even in the device channel set to RESET.
Further more, we have additional questions from the cusotmer.
[Question 2]
Which pin is the leak comming from ?
From VDD pin to OUTx pin or from GVDD pin to OUTx pin.
* I could not read from the Block Diagram.
[Question 3]
Is there any solution to prevent this leak from GVDD or VDD to OUTx ?
[Question 4]
If this leak cannot be prevented, is there any other 3 phase motor driver having similar specification with DRV8332 ? (requires 3Amp continuous current)
* DRV8312 meets current specification, but this is lower current version of DRV8332 which have same behavior with DRV8332.
Best Regards,
Kawai
Hi Kawai-san,
I don't have the answers for questions 1 through 3 at this time. More research into the circuit will be required.
For question 4, I saw similar leakage on the DRV8312. This DRV8312/DRV8332 are very similar in design. I used the DRV8312EVM to determine if the leakage was seen. The leakage appears to be from either the GVDD/VDD through the OUTx pin. I isolated the path from GVDD through the BST_x pin by removing the capacitor from OUT_x, and still saw the voltage appear on OUT_x.
Look for a post once the information is available.
Rick-san,
Is it normal for the device to have voltage output at OUTx pins when in RESET, from design point of view ?
Our customer needs to FIX their schematic by end of this week.
We appreciate if we could have the answers to the questions as soon as possible.
Best Regards,
Kawai
Kawai-san,
I have confirmed this is expected behavior. A path from GVDD through the BST_x diode to OUT_x is created by the high side overcurrent protection logic. The overcurrent protection logic is placed between BST_x and OUT_x. The voltage seen on OUT_x varies depending on the load on OUT_x and PVDD.
Each output will typically leak about 400uA. As you noted, the leakage can travel through the high side body diodes and into the PVDD circuit. Neither FET is enabled during this time.
Being an internal circuit, the only method to remove the leakage is to remove power from GVDD.
Hi Rick-san,
Thank you for the information.
Please let me inform you and ask you some questions.
1)
I have answered the above information to our customer.
They will control GVDD ON/OFF to prevent the leak voltage.
As there is no requirement for the power sequence, I am understanding this usage is not a problem.
Am I correct ? If the may be damage to the device please let us know.
2)
I have confirmed the operation on DRV8312 EVM.
I found that the leak only occurs when the device is in RESET, /RESET_A/B/C pin = Low.
When you set /REST_A/B/C = High there will be no leak to the OUTx.
If the over current protection circuit creates this leak, I think there also should be a leak at normal operation(/RESETx = High). What do you think ?
Best Regards,
Kawai
Hi Kawai-san,
1) You are correct that the there should be no damage.
2) When RESET_x is high, the leakage path can be masked depending on the PWM_x value.
If PWM_x is low, OUT_x is active low and any leakage is to gnd instead of PVDD.
If PWM_x is high, it depends on the value of PVDD again.
If PVDD is powered to greater GVDD - 4 diode drops, there should be minimal leakage.
If PVDD is less than this, the leakage can appear and can be seen by measuring a voltage on OUT_x that is approximately one diode above PVDD.