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Bulk Caps on the DRV8412 GVDD/VDD Pins

Anthony
Prodigy 30 points
Other Parts Discussed in Thread: DRV8412

Hello,

I have a query related to the VDD/GVDD pins on the DRV8412 motor controller. I have a 47uF as well as a 100n decoupling cap by the VDD pin. I'm also using 4x 1uF caps by each of the GVDD pins. I'm runing the IC in parallel full bridge mode @250kHz, with a PVDD of 24V and a VDD of 12V as suggested.

My first query is related to connecting GVDD to VDD. How come this is the preferred option? Given the transients will be generated primarily from the gate drives, could an inductor be used to isolate the regulator input (VDD) from this and reduce the 47uF recommendation?

Similarly, if an inductor is used, what is the suggested bulk cap required as 330uF seems to be a very large value.

Any clarification you could provide on the suggested bulk VDD/GVDD capacitance values would be much appreciated.


Thanks,

Anthony

  • 0
    TI__Guru 55565 points

    Anthony,

    Unfortunately, the pin description shows that VDD only supplies the internal regulators, but there is more to the story.  The 12V guard rings on the output FETs are also tied to this pin and under heavy load conditions, there can by substantial current flowing through the VDD pin. 

    For this reason, we suggest a bulk decoupling capacitor on this pin.  We also suggest sizing your 12V supply to handle currents at least 5% of your intended output current through the bridge and no less than 100mA.  For example, if your target output current was 10A, you would need to budget for 500mA to supply VDD + GVDD currents listed in the tabular data. 

    330uF can be sized down to ~47-100uF.  It is a bit over-kill on the EVM design as we also feed a 5V regulator off this supply. 

     

     

  • 0 in reply to Ryan Kehr
    Prodigy 30 points

    Hi Ryan,

    Thanks for the quick reply.

    So if I'm pulling 4A through the output bridge (using 24V rail), then I should expect a 200mA minimum current draw from the 12V rail? 

    Thanks again,

    Anthony

  • 0 in reply to Anthony
    TI__Guru 55565 points

    Anthony,

    The math is correct and so is your understanding.  However, this is worst case under 125C operation, so you may not see currents this high on the bench at 25C. 

    Typical current into VDD will be closer to 50mA at room temperature.  I just wanted to make sure your regulator could push higher currents under elevated temps.