DRV3201-Q1 SPI(SCLK state when NCS changes high to low)

Toshio Ushikubo

Mastermind 9620 points

Other Parts Discussed in Thread: DRV3201-Q1

Hello,

Please answer following question from customer.

Figure 1. SPI Timing Parameters shows that SCLK is low when NCS changes from high to low.

Please advise what will happen if SCLK is high when NCS changes from high to low.

Best Regards.

over 8 years ago

0 Karl Wallinger over 8 years ago

TI__Genius 16410 points

Hello Ushikubo-san,

Let me move your question to the motor drive forum, as they will be able to answer your question.

Regards,
Karl

0 William Toth over 8 years ago

TI__Expert 3555 points

Hi Ushikubo-san,

We're looking into this now and will have a response by Wednesday.

Regards,
Will Toth

0 William Toth over 8 years ago

TI__Expert 3555 points

Hi Ushikubo-san,

The DRV3201-Q1 device cannot support the case where SCLK is high when NCS changes from high to low.

If you need a more detailed description we can send waveforms to you directly.

Regards,

Will Toth

0 Toshio Ushikubo over 8 years ago in reply to William Toth

Mastermind 9620 points

Hello William-san,

Thank you for your response.
Please send more detailed description to my mail address.

Best Regards.

0 Toshio Ushikubo over 8 years ago in reply to Toshio Ushikubo

Mastermind 9620 points

Hello William-san,

Please send more detailed description to my mail address.
Customer want to know the details of what will happen while SCLK is high when NCS changes from high to low.

Best Regards.

Motor drivers

Motor drivers forum

DRV3201-Q1 SPI(SCLK state when NCS changes high to low)