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At start I read 2A register - default value is 0x018 but I read 0x08.
For a test purpose I write to the register 0x07
write 0x07 - read 0x03
write 0x0F - read 0x07
write 0x09 - read 0x00
So I connected logic analizer and see all signals are good but data on SDATO pin is in phase with SCLK.
But data on the SDATO should be present on falling or rising edge of the SCLK.
This explains why the controller sees one bit less in case of 0111 (0x07) and 1111 (0x0F)
and dosen't see say 0x09 - separated bits.
I have a pull up 10K on SDATO pin.
How should I fix the problem?
I'll try. I should get 4 channel scope.
The first picture - reading from the register 0x2A.
The second one - reading data 0x09 from the register 0x07
As we see the clock signal is good but the SDATO pin returns a bad signal.
It looks like some capacitance on the line. But it's a short conductor between pins and quite strong pull-up 10K.
