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DRV8308: DRV8308

Part Number: DRV8308

Dear Sirs,

We have a design with two DRV8308.

We are adjusting the parameters for differents loads and speeds in very large range. We have a doubt with the Clock Frequency Mode we are using. First it looks a single speed loop PI with some optional automatic gain and advance corrections.

More or less, we are able to choose the parameters for each case in practice, Also we try to replicate the functionality of this speed close-loop mode in a simulation software for faster results.

We have a doubt with the Clock Frequency Mode.

Page 40 of the datasheet:

SPEED parameter: In the the Clock Frequency Mode, SPEED sets the open-loop gain during spin-up before LOCKn goes Low.

What does it mean? It´s not in close-loop mode from the start? The LOOPGAIN, SPDGAIN, and the other parameters, close-loop related, have not influence during spin-up. The duty cycle of the PWM is not calculated from the start until the speed reaches CLKIN?

Thanks and best regards

Javier Vicandi

  • Hi Javier,

    This means that during intital speed-up, the device is operating in strictly Proportional gain mode.  The SPEED register value is the gain applied to the difference taken between the CLKIN frequency and FGOUT frequency.  Once the FGOUT frequency is within the SPDTHD value for a duration of SPDREVS, the device will enter into integral control. 

  • Thank you Phil,
    In the next revision of the datasheet I think it would be useful to include this graph. The real speed is within SPEEDTH before the graphic shown with FGOUT signal.
    Is a resolution issue with the halls?
    To clarify, then LOOPGAIN is the proportional gain, all frequency range, that is applied in the INTEGRAL interval or is it also applied with SPEED gain in the PROPORTIONAL interval?
    The intensity of the integral effect depends off the zero position, set by FILK2, and the SPDGAIN value. It is right?

    Thanks a lot

    Javier Vicandi
  • Hi Javier,

    The LOOPGAIN is the proportional gain at all frequency range that is applied in the INTEGRAL interval. It is not applied with SPEED gain in the PROPORTIONAL interval.

    You are correct that the intensity of the integral effect depends off the zero position, set by FILK2, and the SPDGAIN value.
  • Hi Phil,

    After several tests we have concluded that:
    Neither SPEED nor LOOPGAIN are gains applied to the error signal to calculate the output. If we cancel the integral factor, by doing zero SPDGAIN, and keeping SPEED and LOOPGAIN, the motor speed in the acceleration and steady state are always the same regardless of the setpoint.
    Even the constant speed may be greater than the setpoint, which makes no sense in a proportional regulator.
    In our opinion, SPEED and LOOPGAIN are not gains but constants added to the output. Without integral factor they are directly the output.
    Another thing, LOCKn does not signal the transition from the proportional interval to the integral interval.

    We are wrong?


  • Hi Javier,

    Sorry for the delay. I am picking up the thread for Phil, and will do my best to answer.

    In your previous post, what are your specific questions?
  • Hi Rick,

    The specific question is whether our conclusions are correct or not.
    We are currently closing the speed loop externally, using the microcontroller. We are using the driver in PWM mode.
    We spent a lot of time testing to conclude that we could not use the DRV8308 in closed-loop mode.