DRV8307: Issue with the V_HS and V_LS GDRV

Hi Onkar,

What signal is Channel 1, 2, and 3? Can you zoom in to capture a few (two or three) V_HS cycles with respect to phase V and a few V_LS cycles with respect to phase V.

Please disconnect the load and use Phase U and Phase W to debug Phase V.

The three phases should be identical in operation. Please measure the phase V FETs against the phase U and phase W looking for different resistance from gate to source, gate to drain, drain to source, and source to drain.  

This is V_LS gate waveform

This is phase voltage diagram

Hi Onkar,

The images did not appear. Would you please resend them?

Also what did you observe?
Did you observe any differences between the V phase (signals and resistance) and the U,W phases?