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DRV8436: PWM control interface and Smart Tune (adaptive decay): which takes precedent?

spmcv
Prodigy 140 points
Part Number: DRV8436E

I'm a little confused on the DRV8436P data sheet.

Assume for the moment we have the xDECAY input driven low (smart tune enabled).

I'm assuming for DRV8436E that, at all times, smart tune chooses the optimal decay mode based on xEN duty cycle and xVREF (correct me if I'm wrong).

Furthermore, I'm assuming for DRV8436P if your driving either xIN1 or xIN2 high, smart tune again is choosing the optimal decay mode. So, this is essentially identical to the enable/phase control scheme with exception of 2x the required PWM inputs (again, correct me if I'm wrong).

Now, like most drivers with PWM control inputs, the truth table claims you can explicitly put the H-bridge in slow decay by driving both inputs high.

So, in this case, which takes precedent? If the user specifies slow decay by driving xIN1 and xIN2 high at the same duty cycle, does this override smart tune's choice of decay mode?

  • 0
    TI__Guru 56650 points

    Phuntimes,

     

    When the output reaches the setting current, different decay mode gives different FET on/off option to control the winding current in one PWM cycle.

    In general, xIN1 and xIN2 or EN signal frequency is much lower than the PWM frequency.

    If the user specifies slow decay by driving xIN1 and xIN2 high at the same duty cycle, the DRV8436P will follows the xIN1 and xIN2 signal to make both high FETs on and give the slow decay. Also, the winding current will drop.  

  • 0 in reply to Wang5577
    Prodigy 140 points

    Okay so there is a lot I don't get I assume.

    1. When the output reaches the setting current, different decay mode gives different FET on/off option to control the winding current in one PWM cycle.

    So as I understand it, the internal DLL locks onto the tOFF (or maybe tON?) time. For DRV8436E, the DLL locks onto the falling edge of EN and rising edge of EN which is then defined as tOFF.  During this period, current regulation activates and the course (CCL) or fine (FCL) loops take over. For DRV8436P, this is a little more complicated since IN1/IN2 must both be low, so the falling edge of either IN1/IN2 (whichever later) and rising of either IN1/IN2 (whichever sooner), which is defined as tOFF.  Is this correct?

    2. In general, xIN1 and xIN2 or EN signal frequency is much lower than the PWM frequency.

    Maybe I missed it, but I didn't see a min/nominal/max signal frequency. Could you please tell me what these values are? And what the approximate delta or ratio between the signal frequency and the CCL/FCL frequencies are?

    Thanks

  • 0 in reply to spmcv
    TI__Guru 56650 points

    Phuntimes,

    1. I agree with you. 

    2. Step input can interrupt the Toff. So, if the Step signal change the winding current setting very quick, the driver doesn't wait for Toff to finish and start next duty cycle. So, step input (customer command) has a higher priority than the PWM frequency. In such case, PWM frequency doesn't mean anything. The motor may still run in this case.