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DRV11873: Problem of Lock Detection

Sheng Yang
Prodigy 10 points
Part Number: DRV11873

According to the section 2.4: "Modulate the PWM input between 2 duty cycles 1% to 2% apart. Do this every 1 to 1.5 seconds to prevent the FG frequency matching the internal sampling frequency. The result is an average speed of the two PWM duty cycles." in the documentation "DRV11873 Lock Detection Functionality".

I changed the PWM duty cycles 1% to 2% every 1 to 1.5 seconds, and tried it all the different combinations, however, I still have the lock dection problem. The motor restarts irregularly when the FG frequency falling into the range from about 466Hz to 486Hz. 

Does someone have any suggestion to solve the problem? Thank you so much!

  • 0
    TI__Mastermind 24405 points

    Hi Sheng,

    Thanks for posting your question in MD forum. The workaround that is mentioned in section 2.4 is when target Motor Speed is Variable with FG Inside the False Detect Window. Since your motor is stalling between 466 Hz and 486 Hz, this frequency does not fall within the false detect window. This FG frequency is not a multiple of internal clock frequency of 101.6 Hz and the variation at around 508 Hz (101.6 x 5) is approximately 0.01%. False Lock detection becomes less likely with increase in FG. Are you operating your motor at fixed speed or varying speed? Did you choose the correct CS resistor?

    Regards,

    Vishnu