This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8906-Q1: DRV8906 two channels to be parallel to achieve higher current level--channel to channel delay risks

Part Number: DRV8906-Q1

HI team,

My customer is using the DRV8906 now. Here we want to use two channels to be parallel to achieve higher current level. But not sure about the channel to channel delay( The chip to chip delay is several us. Whether it will cause one channel overcurrent because the on time miss match?) Thanks.

  • Hi Frank,

    To avoid any channel-to-channel delay when using channels in parallel, map the parallel channels to the same PWM channel.  This will avoid the chance of triggering an OCP event.  The data sheet mentions this in section 8.3.1.1.4 Parallel Mode (PWM Operation).

    Regards,
    Mike