DRV8912-Q1: DRV8912 SPI timing tSC_SPI - what is it?

That is what is unclear to me. It would make sense that the minimum SCS high time of 600ns would be the parameter which ensures a minimum time between either reads or writes. Is the write gap an additional requirement?

The name "write gap" is confusing and raises additional questions: If there is a minimum time between successive writes, why is this parameter only given as a nominal value instead of a minimum? What is the write gap referring to - a minimum time between SCS going low on successive writes? Or something else?

It is a concern for me because I am doing multiple writes to multiple daisy-chained devices.

Mitch,

I am digging into this.  I am not seeing this specification in any of our other motor driver datasheets, so I am trying to understand the reasoning here on this device.  Please give me some more time.  

Regards,

Ryan