DRV8303: Minimum required time for EN_GATE activation when reseting faults

Clément Letonnelier

Part Number: DRV8303
Other Parts Discussed in Thread: TMS320F28377D

Hi,

When manipulating the EN_GATE signal, we did find in the datasheet the maximum time we should not exceed in order to avoid putting the device in sleep mode.

However, we didn't see any minimum time requirement for this signal to be taken into account when deactivating/activating it to reset internal faults.

Could you please tell us what is the minimum duration required from the pulse to reset internal faults ?

Best Regards,

Clément

over 5 years ago

0 James Lockridge19 over 5 years ago

TI__Genius 14485 points

Hello Clément,

I'm following up our design team regarding your question.

0 Clément Letonnelier over 5 years ago in reply to James Lockridge19

Expert 2426 points

Hello James,

Thanks. When do you think they will get back at you ?

Clément

0 James Lockridge19 over 5 years ago in reply to Clément Letonnelier

TI__Genius 14485 points

Clément,

I apologize for the delay. We do not have this data on hand, so I will need to investigate some more with my team. I hope to have an answer to you before the end of next week.

0 Clément Letonnelier over 5 years ago in reply to James Lockridge19

Expert 2426 points

Hi James,
Thanks for following up on this.
Looking forward to your answer,
Clément

0 James Lockridge19 over 5 years ago in reply to Clément Letonnelier

TI__Genius 14485 points

Hi Clément,

I will need to develop a bench setup to test this. I tried to take a bench measurement, but I need a better setup than what I was able to construct this week. Unfortunately, this will take more time, so I may not have results to you until next week. I apologize for the delay.

In the meantime, are you able to write the GATE_RESET bit instead for your application, or at least for any testing you need to do?

0 Clément Letonnelier over 5 years ago in reply to James Lockridge19

Expert 2426 points

Hi James,

Writing the GATE_RESET could indeed be a potential solution.

Though the manipulation of the DRV_EN pin would be more convenient in our software architecture

Clément

0 James Lockridge19 over 5 years ago in reply to Clément Letonnelier

TI__Genius 14485 points

Clément,

I was able to clear the fault with an EN_GATE pulse as short as 40 ns. The signal generator I was using would not let me go faster than that.

Thanks for your patience while I investigated this.

0 Clément Letonnelier over 5 years ago in reply to James Lockridge19

Expert 2426 points

Hi James,

Thank you for your investigations.

I understand that you only got that information from tests, there is no input from the design team that would limit this to min/max ranges to ensure 40ns works in all cases ?

Clément

0 James Lockridge19 over 5 years ago in reply to Clément Letonnelier

TI__Genius 14485 points

Clément,

I'm following up with our design team to see if they can recommend a factor of safety on my measured value. How fast do you need the pulse to be?

0 Clément Letonnelier over 5 years ago in reply to James Lockridge19

Expert 2426 points

James,
Well we could deal with the 40ns if that's safe.
Basically we would be doing a clear and a set of a GPIO of the TMS320F28377D, so I think without NOP this would lead to something like 4 to 6 cycles so 20ns to 30ns.
Clément

0 James Lockridge19 over 5 years ago in reply to Clément Letonnelier

TI__Genius 14485 points

Clément,

Our digital designer told me that 100 ns should be sufficient to accommodate all cases.

0 Clément Letonnelier over 5 years ago in reply to James Lockridge19

Expert 2426 points

James,
Thanks for the follow-up/answer.
Clément

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DRV8303: Minimum required time for EN_GATE activation when reseting faults