Hi,
Could you tell me what the expected output voltage is on OUT_X when the reset lines are asserted?
We're currently seeing ~10.5V whilst the reset lines are LOW, with VDD/GVDD_X = 12V and PVDD_X = 18V.
I can't find mention of this in the datasheet and couldn't see from the diagrams where this voltage would be coming from.
Thanks,
Joe