This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8662: Coupling capacitor

Part Number: DRV8662

Hi team,

My customer is evaluating the DRV8662EVM. Could you please support the following questions?

1)  A 2 V offset voltage is observed at the input after the coupling capacitor (C4, C5). Therefore, if JP2, JP3 is removed, in+ and in- are fixed at 2V respectively. So is there an internal circuit that offsets the input of the DRV8662?

2) I think there is a statement in the data sheet that a coupling capacitor should be inserted for IN + and IN-. The evaluation board also follows the instructions. I want to drive a piezo actuator with a 50Hz square wave. Is it okay to remove the above coupling capacitor? Or, I would appreciate it if you could tell me the know-how for driving the above.

Regards,

Yamaguchi

  • Hello Yamaguchi-san, 

    I am looking into your questions and will respond as soon as possible. 

    Best Regards, 

    Justin Beigel

  • Hello Yamaguchi-san, 

    The DC operating point of the input stage on the DRV8662 is set internally so the AC coupling capacitors (C4/C5) need to be there to remove any DC offset between the chip and the input waveform. 

    You can try using larger capacitors to minimize the impact on the 50Hz square wave input. 

    Best Regards, 

    Justin Beigel

  • Hello Justin-san,

    Thank you for the answer. I got the feedback from the customer. Could you please help with the additional question below?

    "You can try using larger capacitors to minimize the impact on the 50Hz square wave input." 

    -->If the input signal has a small DC offset, is it ok to input directly without a coupling capacitor?

    Regards,

    Yamaguchi

  • Hello Yamaguchi-san, 

    It is not recommended to input a signal without the capacitors. This creates the potential for unexpected behavior from the device. 

    Best Regards, 

    Justin Beigel

  • Hi Justin-san,

    Thank you for your support. I explained that we don't recommend to input a signal without the capacitors to the customer. Then, I received following feedback from the customer. Could you please advise to the question below? 

    Could you please explain in detail why it may behave unexpectedly?  Regarding the noise, I believe that the LPF can cut it. I believe that the coupling capacitor is the role of the HPF, and its main role is to set the offset voltage to 0. What kind of behavior are you concerned about when inputting a signal with an offset voltage of 0? If the capacitance of the coupling capacitor is increased in order to input a 50Hz square wave, it will take some time for the offset voltage to reach zero. In other words, the signal is input to the IC with the offset voltage applied. I feel that this is more dangerous.

    Regards,

    Yamaguchi

  • Hello Yamaguchi-san, 

    The DRV8662 sets the DC operating point for the input and may not be 0 volts. So not having the capacitor there gives concern that an input voltage not centered around the same DC voltage won't have the gain properly applied or could get offset on the output. 

    Best Regards, 

    Justin Beigel

  • Hello Justin-san,

    Thank you so much for the answer. Am I correct in understanding that the IC automatically sets the DC operating point? In that case, a coupling capacitor is necessary, isn't it?

    Regards,Regards,

    Yamaguchi

  • Hello Yamaguchi-san, 

    Yes, the IC automatically sets the DC operating point. The coupling capacitor needs to be there so that any DC offset on the input signal that doesn't match that operating point is removed. 

    Best Regards, 
    Justin Beigel

  • Hi Justin-san,

    Thank you so much for the answer. I understand.

    I received another question from the customer as follows. Could you please advise me? 

    Normally, I think the INPUT signal should be input after EN is turned ON.
    Is it OK to input the INPUT signal with EN turned OFF?

    To drive at low frequency, the capacitance of the coupling capacitor is increased.
    Due to this effect, it takes time for the offset component of the input signal to become completely zero.
    I would like to apply the input signal while EN is OFF, and turn EN ON at the timing when the offset voltage becomes 0.

    Regards,

    Yamaguchi

  • Hello Yamaguchi-san, 

    It is best to send a 50% input before the EN pin is turned on. Normally there is a 2ms wait after the EN pin is turned high but if that is not enough time for the input to settle, then the wait time can be increased a little to allow the input to settle. 

    Best Regards, 

    Justin Beigel

  • Hello Justin-san,

    Thank you for the answer. Please let me check my understanding. It's ok to input the input signal during EN is OFF. It is best to send a 50% input before the EN pin is turned on.  Is my understanding correct?

    Does the 50% mean 50% duty cycle? Your suggenstion is same meaning as the 8.4.1.1 PWM Source in the d/s?

    8.4.1.1 PWM Source

    1. Send 50% duty cycle from the processor to the DRV8662 input filter. This is to allow the source and input filter to settle before the DRV8662 is fully enabled. At the same time (or on the next available processor cycle), transition the DRV8662 enable pin from logic low to logic high.

    2. Wait 2 ms to ensure that the DRV8662 circuitry is fully enabled and settled.

    Regards,

    Yamaguchi

  • Hello Yamaguchi-san, 

    Yes, your understanding is correct. and Yes, 50% does mean 50% duty cycle. 

    Best Regards, 

    Justin Beigel

  • Hi Justin-san,

    Thank you for your support. I recieved the feedback from the customer. Could you please help with the questions below? Sorry to the many questions.

    1. It is best to send a 50%(duty cycle) input before the EN pin is turned on. 

    -->Could you please explain the reason why it is best to send a 50%(duty cycle) input before the EN pin is turned on? Does the input mean IN+?

    2. Normally there is a 2ms wait after the EN pin is turned high but if that is not enough time for the input to settle, then the wait time can be increased a little to allow the input to settle. 

    -->Does increasing the wait time mean increasing the time that the EN pin is low? 

    3. 8.4.1.1 PWM Source in the d/s ; 3. Begin and complete playback of the haptic waveform. The haptic waveform PWM should end with a 50% duty cycle to bring the differentialoutput back to 0 V.

    -->Can you please give me more details about this description as well?
    I've interpreted it as if the differential output goes to 0V when the input PWM duty is set to 50%, but I think that's wrong, so I'd like to know the correct interpretation.

    Regards,

    Yamaguchi

  • Hello Yamaguchi-san, 

    1. The 50% duty cycle allows the source and input capacitors to settle before the DRV8662 is fully enabled. In other words, it gives time for the capacitor to charge with the DC offset between source and device input. 

    2. The delay is after the EN pin is pulled high and before the input source starts. This gives time for the input capacitor and the boost voltage to settle before outputting a waveform. 

    3. The goal here is to put the same input as step 1 and allowing the DRV8662 to settle before powering it down. The timing is not as critical so we do not need to add a 2ms wait this time. 

    Best Regards, 

    Justin Beigel