LP5036: About clock function on I2C control

hi Monet, could you help in this case.

Hi Frank, Monet

I got more clear image of waveform.

We recognize two kinds of abnormal pulse in follow figure, A and B.

The clock frequency is 100kHz

Follow figure is overall. The waveform A is constant per 50u sec.

We want to know this pulse can happen by ether this device or STM32.

Best regards,

teritama

Hi Monet, could  you help in this case.

Hi Teritama,

Did you set the Auto_Incr_EN to 1?

Could you please capture the I2C timing Parameters?

Best Regard

Monet Xu

Hi Monet,

Thank you for reply.

I'd like to get confirmation about Auto_Incr_EN and timing parameter to customer.

If the customer set the Auto_Incr_EN to 1 or I2C timing parameter is out of  timing requirements in datasheet, is it possible to occur A or B waveform?

Or does this device have any clock control function?

Best regards,

teritama

Hi Teritama,

If the Auto_Incr_EN is set to 1, the SCL for device will not occur A waveform or B waveform. It is mainly caused by MCU signal. 

And the unexpected I2C timing parameter may cause the abnormal waveform. I suspect the problem is caused by the master device and I2C timing parameter can help us to check some details. And if there is convenient for you please use another master device to communicate with LED driver.

The device works as an slave device so the clock is provided by master device. 

Best Regard

Monet Xu

Hi Monet,

Thank you for quick reply.

I understood you say. I'd like to check these point to the customer.

Additionally, I found about A waveform In follow figure.

It seems that the Hi time of the SDA signal when transmitting the ACK signal is different like follow figure.

Do you think this SDA signal concern A waveform? If this signal concern A signal, I think it will be one of the rationale for determining that the MCU is the cause of this problem.

Best Regards,

teritama

Monet, please help to keep following this question.

Hi Teritama,

It doesn't matter. You can refer to the Figure 18 in the datasheet of LP5036. The 9th clock pulse for acknowledgment correspond to the low level SDA which shows the successful ack signal.

Best Regard 

Monet Xu

Hi Monet,

I understood this device pull down SDA signal during the 9th clock pulse.
I worry about that the SDA signal's high time is different between Nomal and A in upper figure.
Is this due to the timing of pull down SDA signal being delayed?

I want to know this difference is matter or not.

Best regards,

teritama

Hi Monet, please keep following in this case.

Hi teritama,

According to I2C protocol, data don't transfer when SCL is pull down. So the different high time of SDA doesn't matter.

Best Regard

Monet Xu

Hi Monet,

Thank you for your help.

Our customer found this problem is caused by master device.

There is additional question.

In I2C bus, there are some NACK signal.

We think NACK signal is caused by incorrect address specification.

Is it possible that NACK signal is caused when right address specification?

Best regards,

teritama

Monet please keep following this case

Hi Monet, 

I would appreciate it if you could reply.

Please let me know if you need more information concerning this matter.

Best regards,

teritama