This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello Guys,
Good day.
Our customer found that the datasheet for the tps386000 has a bug. In the datasheet, Figure 31. TPS386040 Block Diagram has inverters at the four nRESET outputs. According to him, this is not correct as indicated by Tables 1-4. There should be no inverters there. For example, according to Table 2, when SENSE2 < V_ITN, the nRESET2 output is Low. However the block diagram indicates it should be High in this case, due to the inverter. So Tables 1-4 and Figure 31 contradict one another, and he believe it is Tables 1-4 that are correct.
Could you help to confirm this?
Thanks and regards,
Art
Hi Art,
The block diagram is just a descriptive representation of the IC. The delay block may have some inversion going on that is not shown in the block diagram. Not everything in the IC is represented in the block diagram for the sake of confidentiality.
Tables 1-4 are correct and the customer should follow the tables for exact operation of TPS386000/40.
I hope I have answered your question.
Ben