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BQ76200: Vgs drops to zero on turning ON the load.

vinay kambappa
Prodigy 160 points
Part Number: BQ76200
Other Parts Discussed in Thread: BQSTUDIO

Hi,This is the wave form across gate and source of discharge/charge FET,when enabled using FET_enable on bqstudio.The only difference between FET_enable and DSG_Toggle is that in FET_EN enables both CHG_FET and DSG_FET are turned on simultaneously.

Fig 2

Fig 3

This is when DSG_Toggle was used.

What could be the reason for this behavior? Also I am not using Q1 and Q2 FETS so they are not connected.I am using only Q5 charge FET and Q6 discharge FET.

Initially  turning on the CHG and DSG FET i e (Vgs=10.5V) and when load was turned on Vgs dropped to 0V. Later on replacing the FET the issue was fixed. I was able to discharge the pack at 15A for few minutes then I observed the oscillation similar to the fig2  and then the MOSFET turned off. Later on disconnecting the MOSFET  from the driver ie(by removing R18,R20,R22,R23) and checking the CHG and DSG there was no output voltage although DSG_EN and CHG_EN were high.(I believe the driver is damaged). What is the reason for such oscillations and driver damage?

I am using 470nf capacitor for Cvddcp as per the table given in the data sheet. (The input capacitance of MOSFET is 13000pf ). A series gate resistor of 300E. Could this behavior occur if the Cvddcp is less or the series resistor is large. Or are there any other operation modes of the gate driver where the output is disabled.

  • 0
    TI__Guru 54715 points

    Hi Vinay,

    See the application note https://www.ti.com/lit/pdf/slua794.  The charge pump appears to be overloaded in your first picture.  The part has a UVLO feature which turns off the drivers when the VDDCP voltage drops.  It seems the load of 1 FET is ok but both FETs must pull the part into UVLO.

    I'm not sure I understand or can read the resistor values clearly.  The R18, R19 resistors should be large so that most of the voltage from the drivers goes to the gate of the FET.  The R20, R22 resistors should be a don't care in your described configuration.  R21 and R23 will be series resistors from the driver to the FET gates, these should isolate the driver from any load transients on the battery bus and should likely not be smaller than 100 ohm. 

    The driver should not care that it goes into UVLO and recovers, it will just switch.  The switching action on the FET may cause heating of the FET.  

    With a 13 nF Ciss  the recommended minimum CVDDCP would be 13 x 23.5 = 306 nF, so the 470 nF should switch fine.  With both FETs switching at the same time 13 x 2 x 23.5 = 611 nF, so switching may not work, and that seems to be what you describe.   I'm not certain of the 300E resistor designation, 300 ohms should be in the range mentioned in table 1 of the application note above and allow successful operation.

    You might try a larger CVDDCP value. If the driver has been damaged, you might explore to see how that may have occurred.  Be sure the FET or driver output are not oscillating at turn on.   See the Zener and 100 ohm suggestion in the application note if needed. If you do use both FETs, you will want resistance from the driver to the common drive point for the FETs.