Hi team,
My customer has the following question:
How does the driver drive the high-side FET with HV ~48V when VDD has to be <18V? I.e. how does the gate driver function? Does it use a charge pump or something to generate voltages higher than VDD, or does it take power from HV to drive the gates?
The follow-up question is then: If it uses VDD to charge the driver, can the high side of the bridge be driven indefinitely or only until the charge on the capacitor runs out (or until VDD is overloaded)?
Do we have any documentation/app notes that would cover this topic, or is there a section in the datasheet where this is explained in detail that I could refer them to?
Thanks,
Lauren
