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TPS546D24AEVM: EVM configuration problems

Part Number: TPS546D24AEVM
Other Parts Discussed in Thread: TPS546D24A, TPS546D24


I'm using the TPS546D24AEVM-2PH to test configurations before programming actual boards. I am running into some problems:

  • The power controller is reporting an IOUT of about 22 A, even though the actual IOUT is only about 1.6 A. The input and output voltage reported by the power controller are correct. Also, the IOUT reported by the phases is assymetrical with PH1 = 16.5 A and PH2 = 5.5 A. (IOUT_CAL_GAIN = 1 and IOUT_CAL_OFFSET = 0.)

  • The IOUT UC Fault alert is active. I see no threshold setting for this in the register set and cannot understand what would qualify as an undercurrent.

  • I had to set all FAULT_RESPONSEs to "Continue Without Interruption" to keep the controller from hiccuping. After the output became stable, I changed the FAULT_REPSONSEs again to "Shut Down Immediately" and the output remained unaffected. I don't know which FAULT_RESPONSE caused the hiccuping.

  • Although set to 400 mV output in the NVM, the power controller frequently defaults to 800 mV output. NVM values do not seem to stick.

I have read through the EVM user manual and power controller register descriptions. The EVM is in the factory default configuration. All of the register values make sense. OPERATION and ON_OFF_CONFIG are at default values. VOUT_SCALE_LOOP is 1, FREQUENCY_SWITCH is 325 kHz. I am using Absolute Data Format for VOUT_MODE and E-12 linear format.
Please help me to debug these issues. Thank you!

  • The power controller is reporting an IOUT of about 22 A, even though the actual IOUT is only about 1.6 A. The input and output voltage reported by the power controller are correct. Also, the IOUT reported by the phases is assymetrical with PH1 = 16.5 A and PH2 = 5.5 A. (IOUT_CAL_GAIN = 1 and IOUT_CAL_OFFSET = 0.)

    This is an unusually high READ_IOUT error and phase to phase offset current error.  Much smaller values, less than 3A, are common, but this suggests unstable operation, possibly due to incompatability between the switching frequency, compensation and power-stage hardware.

    The IOUT UC Fault alert is active. I see no threshold setting for this in the register set and cannot understand what would qualify as an undercurrent.

    IOUT_UC_FAULT is reported when the low-side FET current flowing from PGND to SW is more negative than it's threshold of -20A.  The threshold level is not-programmable and the fault response is to terminate the low-side ON time in order to prevent the build-up of a more negative inductor current.  The inductor current is forced through the high-side FET back to PVIN during this time.

    It is a protection feature built into the device to prevent the buildup of excessive negative current in the the inductor, which could become destructive when the low-side FET turns off and the inductor current is forced into PVIN through the body diode of the high-side FET.  IOUT_UC_FAULT being flagged further suggests unstable operation.

    I had to set all FAULT_RESPONSEs to "Continue Without Interruption" to keep the controller from hiccuping. After the output became stable, I changed the FAULT_REPSONSEs again to "Shut Down Immediately" and the output remained unaffected. I don't know which FAULT_RESPONSE caused the hiccuping.

    When you say, the output "remained unaffected" do you mean that output did not hiccup after you changed the fault responses, or that it returned to the prior operation of repeatedly hiccupping once the fault responses were reset to normal?

    Although set to 400 mV output in the NVM, the power controller frequently defaults to 800 mV output. NVM values do not seem to stick.

    1) Did you update the PIN_DETECT_OVERRIDE (Command Code EEh) to clear the VOUT_COMMAND bit (bit 0) to switch VOUT programming from Pin Detection to NVM?

    2) After updating VOUT_MODE, VOUT_COMMAND, VOUT_SCALE_LOOP, VOUT_MIN and PIN_DETECT_OVERRIDE, did you also execute the STORE_USER_ALL command (Command Code 15h) to store the changes in to NVM for future power cycles?

    3) How is the VSEL pin terminated on the board?

    I have read through the EVM user manual and power controller register descriptions. The EVM is in the factory default configuration. All of the register values make sense. OPERATION and ON_OFF_CONFIG are at default values. VOUT_SCALE_LOOP is 1, FREQUENCY_SWITCH is 325 kHz. I am using Absolute Data Format for VOUT_MODE and E-12 linear format.
    Please help me to debug these issues. Thank you!

    These are not "default" configuration settings.

    When you updated the switching frequency, did you also update the COMPENSATION_CONFIG settings to accommodate the slower switching frequency?  The Default compensation settings are not stable when used at 325kHz.

    The first thing I would recommend would be changing the switching frequency back to the default of 550kHz and determining if that restores stability and expected operation.  If not, we can look more deeply into the current configuration and why it's not stable.

    • Please see inline.

    Peter James Miller replied to TPS546D24AEVM: EVM configuration problems.

    Kirk @ Esperanto said:

    The power controller is reporting an IOUT of about 22 A, even though the actual IOUT is only about 1.6 A. The input and output voltage reported by the power controller are correct. Also, the IOUT reported by the phases is assymetrical with PH1 = 16.5 A and PH2 = 5.5 A. (IOUT_CAL_GAIN = 1 and IOUT_CAL_OFFSET = 0.)

    This is an unusually high READ_IOUT error and phase to phase offset current error.  Much smaller values, less than 3A, are common, but this suggests unstable operation, possibly due to incompatability between the switching frequency, compensation and power-stage hardware.

    • Better (-0.65 A indicated) with 550 MHz switching frequency, except that current is now negative.

    Kirk @ Esperanto said:

    The IOUT UC Fault alert is active. I see no threshold setting for this in the register set and cannot understand what would qualify as an undercurrent.

    IOUT_UC_FAULT is reported when the low-side FET current flowing from PGND to SW is more negative than it's threshold of -20A.  The threshold level is not-programmable and the fault response is to terminate the low-side ON time in order to prevent the build-up of a more negative inductor current.  The inductor current is forced through the high-side FET back to PVIN during this time.

    It is a protection feature built into the device to prevent the buildup of excessive negative current in the the inductor, which could become destructive when the low-side FET turns off and the inductor current is forced into PVIN through the body diode of the high-side FET.  IOUT_UC_FAULT being flagged further suggests unstable operation.

    • No error indicator with 550 KHz switching frequency.

    Kirk @ Esperanto said:

    I had to set all FAULT_RESPONSEs to "Continue Without Interruption" to keep the controller from hiccuping. After the output became stable, I changed the FAULT_REPSONSEs again to "Shut Down Immediately" and the output remained unaffected. I don't know which FAULT_RESPONSE caused the hiccuping.

    When you say, the output "remained unaffected" do you mean that output did not hiccup after you changed the fault responses, or that it returned to the prior operation of repeatedly hiccupping once the fault responses were reset to normal?

    • It ceased hiccupping when I switched to “Continue Without Interruption” and did not resume hiccupping when I switched back to the original setting of “Shut Down Immediately.” There is no hiccupping with the 550 kHz switching frequency.

    Kirk @ Esperanto said:

    Although set to 400 mV output in the NVM, the power controller frequently defaults to 800 mV output. NVM values do not seem to stick.

    1) Did you update the PIN_DETECT_OVERRIDE (Command Code EEh) to clear the VOUT_COMMAND bit (bit 0) to switch VOUT programming from Pin Detection to NVM?

    2) After updating VOUT_MODE, VOUT_COMMAND, VOUT_SCALE_LOOP, VOUT_MIN and PIN_DETECT_OVERRIDE, did you also execute the STORE_USER_ALL command (Command Code 15h) to store the changes in to NVM for future power cycles?

    3) How is the VSEL pin terminated on the board?

    • How do I execute STORE_USER_ALL using the TI Fusion tool?
    • VSEL is connected to AGND through a 14.7 kΩ resistor, the default value on the EVM. I have not modified the EVM.

    Kirk @ Esperanto said:

    I have read through the EVM user manual and power controller register descriptions. The EVM is in the factory default configuration. All of the register values make sense. OPERATION and ON_OFF_CONFIG are at default values. VOUT_SCALE_LOOP is 1, FREQUENCY_SWITCH is 325 kHz. I am using Absolute Data Format for VOUT_MODE and E-12 linear format.
    Please help me to debug these issues. Thank you!

    These are not "default" configuration settings.

    When you updated the switching frequency, did you also update the COMPENSATION_CONFIG settings to accommodate the slower switching frequency?  The Default compensation settings are not stable when used at 325kHz.

    The first thing I would recommend would be changing the switching frequency back to the default of 550kHz and determining if that restores stability and expected operation.  If not, we can look more deeply into the current configuration and why it's not stable.

    • Are the compensation settings (CZI, CPI, RVI, CZV, CPV) strictly internal to the power controller? Figure 23 in the TPS546D24A makes it appear this way.
    • Finally, is the register set in the TPS546D24 (non A) any different? That’s all we were able to source in the current semiconductor crunch.
  • Hi,

    Peter is looking into this. Will feedback to you on Tuesday US time.

    Thanks,

    Lishuang

  •  

    I am glad that we were able to find the source of your issues and increasing the switching frequency to 550kHz addressed most of the issues you were having.  That is good news.

    Regarding your follow-up questions:

    How do I execute STORE_USER_ALL using the TI Fusion tool?

    In the FUSION GUI, after selecting a specific device, use the tabs on the lower left to navigate to the Configure View, and at the top of the screen you will see an option to "STORE Config to NVM" - clicking on that button will execute the STORE_USER_ALL command within the GUI.

    VSEL is connected to AGND through a 14.7 kΩ resistor, the default value on the EVM. I have not modified the EVM.

    14.7kΩ to AGND with no resistor to BP1V5 is Resistor Code 6, which programs VOUT = 0.8V with VOUT_SCALE_LOOP = 0.5.  To change the VOUT setting via PMBus, including updating the VOUT_MODE for Exponent -12 and Absolute Mode, you will want to:

    1) Write VOUT_MODE to 14h (Note - VOUT_MODE is read-only while the converter is enabled.  To update it live, you will need to disable conversion with the EN/UVLO pin or the OPERATION Command)

    2) Write VOUT_SCALE_LOOP to 1.0  (Note - VOUT_SCALE_LOOP is read-only while the converter is enabled.  To update it live, you will need to disable conversion with the EN/UVLO pin or the OPERATION Command)

    3) At this point, use the "Write to Hardware" button on the upper left of the configuration window to update these two values to the TPS546D24A device.

    4) Update VOUT_COMMAND to the desired voltage. If you are entering HEX values, remember the HEX is now using exponent -12

    5)Update Pin Detect Override to change VOUT control to NVM on power-up

    6) Write these changes to hardware as Step #3

    7) Store the current PMBus settings to the NVM for future power on reset cycles.

    Are the compensation settings (CZI, CPI, RVI, CZV, CPV) strictly internal to the power controller? Figure 23 in the TPS546D24A makes it appear this way.

    All of the compensation components are internal.  They are selected through PMBus or the Pin Strap setting of the MSEL1 resistors, as defined by the COMPENSATION_CONFIG bit  in PIN_DETECT_OVERRIDE command.

    While the COMPENSATION_CONFIG value can be written or stored to NVM while the converter is enabled, the internal components will not be updated live with the output enabled to prevent the output from becoming unstable as the compensation is updated.  To update the compensation you can either disable the output through the EN/UVLO pin or the OPERATION command, as set by the ON_OFF_CONFIG command.  Otherwise, you can write the new compensation, store it to NVM and cycle the AVIN power to trigger a new Power On Reset.

    Finally, is the register set in the TPS546D24 (non A) any different? That’s all we were able to source in the current semiconductor crunch.

    The TPS546D24 contains a sub-set of the commands supported by the TPS546D24A, and it used different programming resistors to select similar configuration settings.  In addition, the TPS546D24's pin-strap function is only intended for initial power-up during production.  As part of the production flow, these settings should be committed to NVM and the PIN_DETECT_OVERRIDE command should be set to 0000h

    I would recommend only using the TPS546D24 for pre-production / engineering testing and the TPS546D24A for production.