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TPS65000-Q1: UVLO behavior

Piotr F.
Intellectual 2490 points
Part Number: TPS65000-Q1

Hello Experts,

Can you help to understand what happens to TPS65000-Q1 DC/DC output when VINDCDC rises up (system starts) and falls down (system shuts down) in <0V - >=2.3V> range?

Datasheet gives:

UVLO at 1.72V ~ 1.82V

VINDCDC as 2.3V min.

So it is not clear how IC DC/DC behaves in the <UVLO - >=2.3V> range. 

If it helps please account for DC/DC Vout set to 1.8V. 

This is needed for syste FuSa evaulation.

Piotr 

  • 0
    TI__Genius 10380 points

    Hi Piotr,

    I'm assuming EN_DCDC is tied to VINDCDC. Below the UVLO threshold, the device is off or the VOUTDCDC output discharge is enabled, pulling VOUTDCDC down to GND. Once VINDCDC crosses the UVLO threshold, the output voltage ramps up to VINDCDC. If VOUTDCDC is set to 1.8 V, the output voltage regulates to 1.8 V as VINDCDC continues to ramp above 1.8 V. However, due to the limited headroom (VINDCDC - VOUTDCDC), it is not recommended to apply any load until the minimum VINDCDC is reached (2.3 V). 

    Thanks,

    Gerard