BQ76952: BQ76952: BMS Design Review

Hi Max,

30 FETs is a lot of FETs. UCC27524DR is a capable driver but you should likely get an opinion from the experts on that product, I will see if they can look at it.  You should see how well the FETs respond to parallel operation.  With many in parallel you may need to take care in routing, with a low resistance from the driver (R87), you likely want the individual gate resistors to be small (R6, R18, R27, etc), this may be a good application for a bead which has low DC resistance and high impedance at high frequency to avoid oscillation.

The basic topology is like the application note, so it should function similarly other than component selection, layout, and load differences.  On the charge circuit the Q48 base current will be only about 12 uA peak, so the turn off may be slow.  R79 may need to be much smaller, perhaps R83.  With many FETs you may have better performance with an isolated driver, obviously that would be more circuitry, but consider what is needed for your application.

The TPS61040DBVR circuit is labeled "Step-Down DC/DC", but it is a boost converter and seems to be connected according to the data sheet.  I do not have experience with that device, if you have questions you might ask on the forum regarding the specific part number.

Note that the BQ76952 has limited range of the SRP and SRN lines.  With the different boards and high currents be sure the sense pins remain within limits to avoid resets.

Thank you for your detailed and fast reply. 

1) Yes, that is what I'm trying to check including the correct value for R87 as it was taken from guess. About ferrite beads - would you recommend specs or even some suitable model as a reference? Should I post this question to a different topic for review with experts in MOSFET driving? 

2) Where I can read more on the proposed isolated driver circuit? If we keep the current circuit, what would be your suggestion on R79 and R83 values?

3) It's a text mistake. Apologies for the confusion, it's a step-up. 

4) Resistor was calculated using proposed formulas but I will definitely check that. 

Hi Max,

This is a lot of FETs to drive with one driver...  Here are things to consider:

1)  What is the maximum speed that these FETs would be switched on and off?

2)  What is the gate charge or total gate capacitance of one of the FETs?

You can also then calculate the power dissipated using the formulas in the datasheet.

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We also have our next-generation drivers that have just been released for sampling and should be available later this year.

We have a single channel 10A/10A Source/Sink (UCC27614) and the updated version of the UCC27254 (UCC27624) 5A/5A.  These new drivers have increased negative voltage handling, high reverse current handling capability, and a lot of transient headroom with a 30V VDD.

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Please let me know if you have any additional questions.

Thanks,

Aaron Grgurich

Aaron Grgurich said:

ted version

Hi Aaron, 

1) Should be as fast a possible. We are going to need to close the power switch at very high currents (>2000A), so it's critical to make it fast, so MOSFETs are not going to damage. The UCC27524 has 6-7nS transition time, so that's about the fastest chips on the market. Would you give us any recommendation on this based on experience? 

2) We are testing several MOS and attached you can find datasheets. TDM3742, AOB280L, HSH8004. Avg total gate charge is about 80nC. 

Would be happy to swap driver IC once more capable modes are released and available in stocks. 

Thank you!

1912111437_Techcode-Semicon-TDM3742_C380239.pdf
AOB280L.pdf
2005081818_HUASHUO-HSH8004_C508813.pdf

Hi Max,

Yes, the UCC27524 is one of the fastest dual-channel gate drivers on the market!

To clarify, the Rise/Fall Time you mentioned is specified using a 1.8nF capacitive load.

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Using the capacitor equation:  C = Q/V

Q = (80 nC) * (30 FETs) 

V = 12 V

--->    C = 200 nF

You have approximately 200nF load on each of the two driver channels.

With this capacitive load, you will have a pretty significant risetime.  The equivalent parallel resistance is approximately 1.6 Ohms.

So your RC time constant would be approximately 320ns.

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Do you have a requirement on FET turn-on / turn-off time?

Will these be switching at any significant frequency?

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You may want to consider using an extra driver or two per bank of FETs depending on your requirements. 

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I look forward to hearing back!

Thanks,

Aaron Grgurich

Hi Aaron,

thanks for the detailed explanation.

99.99% of the time our BMS is going to keep both FET sides open and only in very rear conditions, it will close them in order to protect load or battery. This way it's not going to use any PWM and switching signals except the one pulse that will close FETs.

Regarding turn-on/turn-off time - we don't have any specific value but maybe you can suggest what we should have (your rough estimation)? As said the switch should go off at 2kA load and we don't have a massive heatsink in the system.

Can you also show us how to use two drivers per side? (4pcs total)

Thank you! 

Hi Max,

Okay, I assumed that the FETs would not need to be switched at any significant frequency, so that makes sense (based on the application).

Before we go that route, I am a bit confused, are you using the UCC27524 to drive each bank of the FETs?

Also, I am a bit confused on the schematic and have some questions:

1)  Does OUTA drive one set of FETs and OUTB drive the other set of FETs (Or are you only driving the right side with the driver?)?

2)  Is the driver referencing the same GND as the FETs (their sources)?  This is needed for a proper V_gs on the FETs to turn on and off.

3)  Do you have a specification on how fast the protection needs to kick in (this will give us a good idea of how fast we need the FETs to turn on/off)?

4)  You can tie the inputs together (The traces must be connected as close as possible to the driver, so that they turn on at the same time) and then the output(s) can be connected to even amounts of MOSFET gates (for example, 15 FETs per channel).  You could also consider higher current, single channel drivers such as the UCC27614 or the UCC27322; and then tie the inputs of the separate drivers together.  For this, it will be likely be important to make sure all the traces are very close to the same length.

I look forward to hearing back, thanks!

Aaron Grgurich

Hi Aaron, 

currently, we use only one UCC27524 for both banks as was proposed in the SLUAA84 document but I understand now that we use more FETs, so we need to use more drivers in order to get faster switching as well as have enough capabilities. 

Please find answers below accordingly:

1) Yes, OUTA drives discharge FETs and OUTB drives charge FETs. One driver for both banks (sets). 
2) GND is connected to "PACK_NEG" (R49 jumper) line which is connected to sources of the charge bank. Sources of the discharge bank are connected to the output but it's the same GND line once FETs are opened. 
3) Our system would detect short circuits within 3.3ms, so ideally we need to have an instant reaction on switching FETs off. What time we can achieve by using 2x driver IC on each bank? See next answer as I think we will use the suggested single-channel driver instead. 
4) That is an amazing suggestion. We likely use UCC27614 in configuration two per bank (even connection as proposed). What would be your estimates on switching time using this config and driver IC? Would appreciate it if you can share the calculation, so next time we do the math ourselves. 


Thank you!

Aaron, 

one more question I have is about power supply capabilities. 

How to make sure that our 12V power supply is sufficient for the configuration of the 4x UCC27614 drivers? Can you please explain how to verify that we can supply enough power as if we drive FETs with 7.5A each it requires 30A total current which seems crazy? The same SLUAA84 example uses a 12x FETs + TPS7A4001 regulator that only provides 50mA output, so I'm confused on how it's possible to give enough current for switching FETs. 

Sorry for the silly questions but I'm never worked with high-power FET circuits, so want to completely understand this situation. 

Our setup is having 1.6 Ohm total gate resistance (3.2 Ohm per each 15x FETs). So the max current should be 12V/1.6R = 7.5A per bank, isn't it? 

Also, there was a proposal using ferrite beads instead of resistors. I'd like to understand what advantages we get by using FB instead of a resistor. 

Thank you in advance. 

Hi Aaron,

thanks for the documents - they are very informative. I'm doing my math now but a very quick question - what would be the recommendation when defining switching on/off FET at very high currents?

Trying to understand if there is a possibility to damage FETs when closing it while it carries high-current (2kA)?

Is there any rule of thumb about closing FETs at particular currents? Or maybe it would be possible to explain this in a nutshell?

Let's say I can design a circuit that can switch FETs at 50ns min but should I pursue this time at my currents or it's better to increase it to 500nS and make the design more reliable?

The reason I'm checking this is that our current OEM BMS design sometimes has failure when FETs are burned when entering off state (protection mode) at high currents.

Thanks in advance! 

Aaron, 

noted with thanks. Additionally, I can't find a clear answer on finding two of the specs: peak gate current and external gate resistance. 

Let's say we want to get approx 150ns turn-on/off time, so we have a basic equation that will show us an avg current for the complete transition of the Vgs from 0 to 12V:

- Cg = 74nC 
- FETs = 15pcs (even topology as discussed)

I_avg = 1110nC / 150ns = 7.4A 

What would be the best way to calculate the external resistance needed? As this is an avg current and Vg is also having a non-linear shape, so I'm a bit confused about how is the formula looks like for R_ext. 

The next question is once I have R_ext then we can check the peak gate current that we need to pull from the driver. I belive that would be a simple formula like this: 

I_pk = Vgs / (R_on + R_ext + R_g_int), where
- R_on is the driver's pull-up resistance (I think can be omitted as there is no value on this for UCC27614? See "7.3.4 Output Stage" datasheet section)
- R_ext is external gate resistance (to be defined) 
- R_int is FET gate resistance (1.3 Ohm per datasheet) 

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Here is my calculation and thoughts. Please let me know if I'm right direction of thinking. 

We can do this from the end to the beginning. My wish is to use two UCC27614 per each half of the FET bank. So it limits us to 20A (10A per each IC). Let's leave some room, so take 18A instead for safety. 

This can give us total resistance needed 12V/18A = 0.67 Ohm. Approx R_ext should be 10 Ohm if we do not count the R_on and R_int. 

Is that how it should be selected? 

Thank you! 

Hi Max,

Please allow us some time to review the latest information/questions. We will get back you with an update early next week.

Best regards,

Andy Robles

Hi Aaron,

well noted about I_pk. Thanks!

Regarding resistance - the calculation was made for bank/2, so it's for 15x FETs.

Have a couple of new questions:

1) The "sluaa84" document recommends having a blocking circuit that allows the gate voltage to go negative when the CHG signal is off. For example, "Figure 5-9" has a Q3 circuit that will turn off the CHG FETs at 0.12A current. With my setup of FETs (1110nC), it's going to turn off at about 9.2us (1110nC/0.12A).

I believe that such a circuit should be mandatorily used for the CHG FETs, is this correct? Also, I'm not really clear if such a long turn-off time is OK if I made a calculation correctly. Please let me know your recommendation.

2) I use 9.1 Ohm gate resistance in order to achieve 60ns turn on/off time. This requires an 18.5A (1110nC/60ns) peak current and I'm thinking about a suitable DC/DC solution that will provide enough power. Any recommendation on this? The bottleneck is that our BMS should work at voltages from 9V up to 70V which request buck-boost topology. Would appreciate your suggestion on power regulator ideas.

I remember that this peak current is going to be needed for a very short period of time (0.5-1us) but still not clear on how to select DC/DC that will provide stable output for these spikes.

Thank you!

Hi Max,

These questions are more directed to our BMS Team, so I will let them help you from here.

Thanks!

Aaron Grgurich

Hi Max,

1. The charge FET gate must be able to follow the source to keep the FET off with a charger present.  With the schematic of sluaa84 figure 5-9, see the turn off shown in figure 5-11.  As PACK- goes below GND the gate must also go below GND.  The blocking P-ch FET is a simple way to do that with a GND referenced driver.  In many systems this is fine since the charge current is small relative to the discharge current.  But systems vary, you will know your requirement.  If you have a large charge current you may need a fast turn off for charge.   You may need an isolated driver such as the approach diagramed in Figure 2-5. Isolated Driver.

2. For a BMS the FETs will normally switch infrequently.  Current for the fast switching spike will typically come from the capacitor for the supply, so the ESR of the capacitor must be small as well as the resistance of the driver and the resistance to the gate(s) so that you can get the high current desired. The regulator which charges the capacitor can be slow, certainly fast enough to maintain an adequate voltage for the driver after the large spike from the capacitor, but you should have many choices for a regulator.  I don't have a specific requirement, you might see options at www.ti.com/dcdc.  There will be a different set of experts from Aaron or I.  One caution with a BMS and fast switching, the geometry of a battery system is rather large, fast switching with high currents can result in a large inductive voltage spike which can stress many parts in the system. Fast switching may be exactly what you need, but be sure to consider the inductive response.

Good day!

We almost finished the schematic that I want to share with you but one more question that appears from your answer as well as from Aaron's - what would be the best way to protect the design from such inductive voltage spikes when closing FETs fast at high currents? 

Thank you in advance! 

Hi Max,

You are working with an inductive response V = L x dI/dt.  As Aaron indicates you want to keep L low with large current.  The other thing to control in the equation is dt which would mean to switch more slowly.  Slower switching with a battery may allow current to build to a higher value, so there is a tradeoff.

For a battery the cells may have a fixed inductance and a physical size which may force a loop area, so your inductance may be difficult to reduce.  If you must have fast switching you may need to clamp the resulting transients with some circuitry.

Dear WM5295 and Aaron Grgurich! 

After all our discussions I'm attaching an updated design for the power board first where mainly the FET circuit is designed. Due to very limited space, I had to change my plans and use four single drivers tied together per each FET side in order to get 37A spike current capabilities. Those drivers are going to be located on the logic board. Both power and logic boards are stacked with headers.

Please let me know your thoughts on the power board first, so then I can send an updated logic design for validation.

For this power circuit, I'd like to check if all my comments and circuit logic placed as notes are correct in addition to the general circuit review. 

Thank you in advance!
PWR_REV1.2_SCH.PDF

WM5295 Aaron Grgurich

Just checking guys if you received my last message in this thread as I had no notification from the system this time as I used to have before with other messages. 

Thanks!

Hi Max,

Hopefully, WM5295 will be able to get back to you by the end of the week.

Otherwise, I think we have given you a solid amount of direction at this point.  What driver did you end up going with?

Thanks,

Aaron Grgurich

Thanks Aaron. 

The UCC27614 looks like a perfect choice. 

Hi Max,

For a battery the general circuit construction seems ok. There are many tradeoffs in a system design which may lead to compromises somewhere. 

With your desire for fast switching the voltage that the BMS is exposed to from the V = L x dI/dt is a concern for the circuitry as mentioned in one of the posts above.  Splitting the circuit on multiple boards as you mention certainly may be required for system restrictions.  For fast switching the inductance of the gate loop should be minimized, the same V = L x dI/dt will apply to the gate drive circuit.  Having a compact gate loop with the driver close to the FETs will allow faster switching. 

Some general comments on the notes: The FET selection calculation the 59 V VDS would seem to be the minimum quiescent.  When selecting the FET you will need to accommodate the reversed charger voltage for the discharge FETs as noted in the FET states block at least for the discharge FETs.

R104 will keep the discharge FETs off if the charger is not powered.  It will draw a quiescent current when the FET is on. When the driver turns off the driver should turn off the FETs, so R104 may be a relatively large value if it is desired to keep the current low.

R103 will similarly keep the charge FETs off when the driver is off and discharge the gate(s) after Q54 turns off.  Again it may be a medium to large value.

R87 provides the base current for Q54 to turn off the charge FETs.  Q54 will operate with its hFE.  To get 1.6A if hFE is 100 you need 16 mA of base current.  Select a suitable R87 value for the hFE of the transistor you use.  R87 may be the key value to optimize for your charge turn off.