Hi Team,
Good day! Kindly check our cusotmer's concern below.
I have a couple of detailed operational question on the LM61460 regulator (or any synchronous regulator for that matter) which stems from an attempt to calculate piecemeal the overshoot with a two-stage output filter.
1. If the first inductor has a negative current when the regulator switches on, does that initial negative current flow thru the HS MOSFET back to the source?
2. Assume the regulator is switched on for a short period and then switches off when the error voltage falls below the ramp voltage. Now assume that because of the various currents the error voltage rises faster than the ramp voltage such that it exceeds the ramp voltage at some point within the same cycle. Does the regulator switch on for the second time in the same cycle? Then if the error voltage increase is sufficiently slower does it switch back off for the 2nd time in the same cycle? Etc? If it happens to be ON at the end of the cycle does it simply stay ON for the start of the next cycle?
2A. If my maximum duty cycle is 90% at 500kHZ (guesstimated from the 87% at 1.85MHz in the datasheet) with a cycle period of 2 usec, does the 0.2 usec it has to be off always come at the end of the cycle or is it taken from the sum of the OFF times throughout the same cycle? Or if the duty cycle is greater where does the tOFF minimum (65nsec.) come from in a similar scenario? What is the maximum duty cycle of a LM61460 at 500KHz (not including any foldback)?
3. How long does it take, on average, for a change in V_FB to be seen at the comparator? Is this primarily a function of the compensation network? (If this question gets too involved, forget it.)
Thank you for your support.
Best regards,
Jonathan