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LM61460: Operational Inquiry

Jonathan Navor
Genius 9105 points
Part Number: LM61460

Hi Team,

Good day! Kindly check our cusotmer's concern below. 

I have a couple of detailed operational question on the LM61460 regulator (or any synchronous regulator for that matter) which stems from an attempt to calculate piecemeal the overshoot with a two-stage output filter.

1.  If the first inductor has a negative current when the regulator switches on, does that initial negative current flow thru the HS MOSFET back to the source?

2.  Assume the regulator is switched on for a short period and then switches off when the error voltage falls below the ramp voltage.  Now assume that because of the various currents the error voltage rises faster than the ramp voltage such that it exceeds the ramp voltage at some point within the same cycle.  Does the regulator switch on for the second time in the same cycle?  Then if the error voltage increase is sufficiently slower does it switch back off for the 2nd time in the same cycle?  Etc?  If it happens to be ON at the end of the cycle does it simply stay ON for the start of the next cycle?

2A.  If my maximum duty cycle is 90% at 500kHZ (guesstimated from the 87% at 1.85MHz in the datasheet)  with a cycle period of 2 usec, does the 0.2 usec it has to be off always come at the end of the cycle or is it taken from the sum of the OFF times throughout the same cycle?  Or if the duty cycle is greater where does the tOFF minimum (65nsec.) come from in a similar scenario?  What is the maximum duty cycle of a LM61460 at 500KHz (not including any foldback)?

3.  How long does it take, on average, for a change in V_FB to be seen at the comparator?  Is this primarily a function of the compensation network?  (If this question gets too involved, forget it.)

Thank you for your support.

Best regards,

Jonathan

  • 0
    TI__Guru 50120 points

    Hi,

    1. In a synchronous buck converter, when the high-side FET is off and low-side FET is on, the charge from the output filter capacitors is taken and the current flows negative, sinking into the device. The source sees negative current when the high-side FET turns back on and the input capacitor will sink the current. For more details on mode transition you can refer to this app note (SNVA857) which talks about CCM,DCM and PFM in greater lengths. 

    2. What application will this occur in? Also what are the various currents and where is it coming from? Can you help clarify what situation the application will be in? Here is an app note on output voltage limitations in a buck converter (SLYT293). Figure 2 provides visual on the error amplifier output and PWM ramp in relation to the duty cycle of the application.

    2a. You can use the datasheet frequency dropout curve to estimate the maximum duty cycle. Perhaps you can refer to Figure 10-25 for an application example. The maximum duty cycle to keep 400kHz for a 3.3V output is right at the knee where VIN is around 3.65V for a 3A application. This means the maximum duty cycle is around 90% in this case. 

    3. I do not have insight on the propagation delay of the comparator with the sudden change in V_FB. 

    Regards,

    Jimmy

  • 0 in reply to Jimmy Hua
    TI__Genius 9105 points

    Hi Jimmy,

    Good day! Thank you for your last response however our customer have a secondary question as shown below. 

    I have a secondary question that might alleviate one of my initial questions. I think I just learned that at the start of each cycle the regulator will switch on if the error voltage exceeds the ramp voltage, which is 0 at the start of a cycle. Then when the rising ramp voltage meets the error voltage it will switch off and stay off for the remainder of the cycle no matter what the error voltage changes to. Is this correct? If so it would eliminate my oscillation concern in my second question. Carrying it further, if the error voltage rises faster than the ramp voltage the regulator will stay on until the maximum duty cycle of the regulator is reached and then switch off; if the error voltage is less than 0 at the start of a cycle, the regulator will never switch on and be off the entire cycle. Is this all correct? Thanks for your indulgence.

    Best regards,

    Jonathan

  • 0 in reply to Jonathan Navor
    TI__Guru 50120 points

    Hi,

    The duty cycle is determined by the output of the error amplifier and the PWM ramp voltage. The ON time starts on the falling edge of the PWM ramp voltage and stops when the ramp voltage equals the output voltage of the error amplifier. The output of the error amplifier in turn is set so that the feedback portion of the output voltage is equal to the internal reference voltage. This closed-loop feedback system causes the output voltage to regulate at the desired level. 

    If the output of the error amplifier falls below the PWM ramp minimum, then a 0% duty cycle is commanded, the converter will not switch, and the output voltage is 0 V. If the error-amplifier output is above the PWM ramp peak, then the commanded duty cycle is 100% and the output voltage is equal to the input voltage.

    Regards,

    Jimmy

  • 0 in reply to Jimmy Hua
    TI__Guru 50120 points

    Hi,

    Just wanted to double-check that this resolved your question. 

    If not, what other questions do you have?

    Regards,

    Jimmy