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UCC21530: and all other Digital Isolators & Isolated Gate Drivers

Part Number: UCC21530

Hello!

General question regarding Isolators and Isolated Gate Drivers, I'm referring to app note SLLA284 "Digital Isolator Design Guide", section 4 "PCB Design Guidelines":

In fig. 4-1 it is shown in red colour (= mandatory for correct function as specified in data sheet?) to have no copper at all under the devices.

Questions:

  • What are the exact technical reasons for this recommendation/requirement?
  • Are they isolation related only (creepage etc, as described in the AN)?
  • Or is a deterioration of operating parameters, especially CM transient immunity, to be expected?
  • Does the internal construction of the devices (namely the very small coupling capacitors used for isolation) require that there is no conductive material in close proximity that will possibly add stray capacitance to the midpoint of the 2 caps in series? How sensitive is

I'm asking because in my application it is virtually impossible to have no conductors, more specific, planes under the isolator, but max dv/dt and max reliability is required. On the plus side, I only need functional insulation...

Thanks in advance, Jochen

  • Hello Jochen,

    Thank you for reaching out on E2E!

    As specified in a note on page 36 of the UCC21530 datasheet, the reason to leave out traces below the device is to maintain isolation performance. Such traces should not have significant impact on other performance characteristics. That said, it might be a good idea to minimize high frequency signals under the device to prevent any coupling of noise.

    It is, however, important to make sure you are meeting the isolation requirements you need on a system level, respecting the creepage and clearance needed for your application.

    If this answers your question please let us know by clicking the green button, otherwise please let us know how we can help further.

    Regards,

    Daniel

  • Hello Daniel,

    thanks for your quick reply!

    So you're saying that a continuous gnd plane (more specific: DC-link midpoint) in inner pcb layers under a Digital Isolator / Gate Driver is not changing / degrading the dynamic properties of the devices? That sounds good...

    As said, insulation requirements are only "functional" in our application, and material has high CTI anyway. So creepage / clearance / pollution are not a problem here.

    Thanks again and regards,

    Jochen

  • Hi Jochen,

    Happy to help! 

    The gnd plane you describe should not affect the performance of this driver, and since functional isolation is the goal the design should still meet the requirements.

    Regards,

    Daniel