Hi Ti Team,
We are using TLC5957 LED driver. Below i provided the how we want to use the LED driver.
We will get the Mode & Sub-mode details as input to the FPGA, we want to drive the each LED(16 LEDs totally) based on the mode & sub-mode. It includes below functionality
- Changing the color of each LED
- Toggling each LEDs based on the mode & sub-mode
MODE |
SUB-MODE |
COLORS |
Color Values (48 bit- {B,G,R}) |
Toggling |
A |
1 |
Green |
{0000,FFFF,0000} |
|
2 |
Red |
{0000,0000,FFFF} |
0.2 Hz |
|
3 |
Blue |
{FFFF,0000,0000} |
|
|
4 |
Orange |
{0000,7FFF,FFFF} |
|
|
5 |
Purple |
{FFFF,FFFF,0000} |
|
|
6 |
Yellow |
{0000,FFFF,FFFF} |
0.2 Hz |
|
B |
1 |
Green |
{0000,FFFF,0000} |
|
2 |
Red |
{0000,0000,FFFF} |
1.0 Hz |
|
3 |
Blue |
{FFFF,0000,0000} |
|
|
4 |
Orange |
{0000,7FFF,FFFF} |
|
|
5 |
Purple |
{FFFF,FFFF,0000} |
|
|
6 |
Yellow |
{0000,FFFF,FFFF} |
0.2 Hz |
|
C |
1 |
Green |
{0000,FFFF,0000} |
|
2 |
Red |
{0000,0000,FFFF} |
1.5 Hz |
|
3 |
Blue |
{FFFF,0000,0000} |
|
|
4 |
Orange |
{0000,7FFF,FFFF} |
|
|
5 |
Purple |
{FFFF,FFFF,0000} |
|
|
6 |
Yellow |
{0000,FFFF,FFFF} |
|
Please find the below queries,
- Global Brightness control (BC) : 3 bit à It is meant for the Brightness control of all LEDs at a same time. Please confirm?
- Global Brightness Control (CC) : 9 Bit à It is meant to represent the brightness of each color for all LEDs. Please confirm?
- We are keeping 30 SCLK cycle(idle clock cycle) in between the FCWRTEN command and WRTFC command. We presume it won’t be a issue, Please confirm?
- “During the same period of step 4, GS data for next line should be written into GS data latch. Using LATGS command for loading 48-bit GS data.” à We understand that GCLK is used to set the brightness. So during GS data write (768 bit write operation), we need to provide the GCLK edge from 0 to 65536 rising edge. By that time LATGS command applied, whatever the GCLK edge counter value provided, that value is set as brightness level.
- When new GS data (768 bit) is loaded, do we need to provide GCLK again?(for each new GS data).
Please confirm our understanding w.r.t point 4 is correct or not?
- When LATGS command is provided, we understand GCLK edge counter will be reset. Please confirm?
- We need more clarity on XREFRESH bit. From user guide, we understand below points
- XREFRESH = 0, GCLK must reach 65536, then only GS data from Latch 1 will move to Latch 2.
- XREFRESH = 1, during last line when LATGS is provided, then GS data from Latch 1 will move to Latch 2. During this mode of operation, do we need to provide the GCLK ?
What is the difference in GCLK when XREFERSH = 0 and XREFERSH = 1 ?
- We are not using Poker mode, in this case do we need to use LINERESET command? When it is required for normal mode?
- To blink the LEDs, we understand below methods can be used
- Change GS data to zero (change respective group’s 48 bit data to zero in GS Data latch register)
- Change BC value to zero in FC register
- Change CC value for R,G,B to zero in FC register
Please confirm our understanding is correct or not?
Regards,
Jagan