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LM25149: CNFG pin controlled by application

Petr Zkrat
Intellectual 410 points
Part Number: LM25149

Hello,

datasheet says that active EMI is automatically enabled at 40% of the current limit. However, we are unsure how will conducted emissions look like in our application, at which level they will become over the line, therefore we would like to have it controlled from microcontroller or enabled by default. And here comes the trouble:

This pin is as well used for configuring Spread spectrum, primary/secondary etc. at the startup during the first 50us. Could you propose or share general do's and don't do's?

-When this DCDC is powering up, the rest of the board is still unpowered. I assume that potential CPU control circuit must be tri-stated during the LM25149 start-up in order not to confuse the "power-up configuration" control logic?

-What is the maximum voltage level, is it ok to use VCC as a high voltage level?

-Any safe simple trick that can be used to enable AEF by default, without affecting the power-up configuration? (if we want to skip the MCU control)

Thank you for any tips

Petr

  • 0
    TI__Mastermind 22299 points

    Hi Petr,

    CNFG pin is AEF enable after configuration yes.

    Be sure the AEFVDDA signal is pulled up before 50us configuration starts, generally AEFVDDA is pulled up off of the LM25149 VCC so we recommend doing that.

    The AEF EN signal should be tri-stated during configuration yes. 

    You should be able to use a pullup diode from PG to CNFG to force AEF enabled when in regulation.

    Note when in PFM mode, the VCC cannot source that much current in sleep. If AEF is forced on and pulling VCC current it could increase IQ or trigger a VCC UVLO.

    Hope this helps,

    -Orlando

  • 0 in reply to Orlando Murray
    Intellectual 410 points

    Thanks Orlando!

    I was thinking about pgood, but I was not sure if there could be any glitch at the start-up. Thanks for the tips, I haven't seen the VCC limit in datasheet so I did not thought about it, very good point. I think I will use the PGOOD approach.

    Cheers,

    Petr

  • 0 in reply to Petr Zkrat
    TI__Mastermind 22299 points

    Hey Petr,

    Yes just be sure to use a diode as PG is pulled down strongly.

    Also if you run into VCC UVLO issues you can use a 5V VCCX.

    -Orlando

  • 0 in reply to Orlando Murray
    Intellectual 410 points

    Thanks Orlando. In the end I pulled PG pin to VIN via pullup, which then forms a divider with CNFG resistor (plus the diode between CNFG and PG). That ensures 2-5V at the CNFG over whole required Vin range. 

  • 0 in reply to Petr Zkrat
    TI__Mastermind 22299 points

    Hi Petr,

    I wouldn't recommend a VIN pullup, the PG pin abs max is 6.5V.

    Please pullup to VCC which is up when the device is enabled.

    -Orlando

  • 0 in reply to Orlando Murray
    Intellectual 410 points

    Hi Orlando,

    Thanks for the note, the maximum operating range is ensured in the current circuit. But if there are no differences in behavior of Vcc in PFM, I might switch to that. 

    Btw could you share what is the Vcc current limit that is "ok to use" by AEF in PFM mode? So I can verify when I have board in hand (I will then measure consumed AEFVCC current over whole PFM range). If I see any issues, I might as well use FPWM at lighter loads.   

    Thank you  

    Petr

  • 0 in reply to Petr Zkrat
    TI__Mastermind 22299 points

    Hi Petr,

    Typically I measure 15-25mA AEF VDDA DC current consumption, however this will depend on how much noise AEF is cancelling. 

    The VCC current limit is 170mA (typ) or 115mA (min) as spec'd in the datasheet, however the VCC regulator is not fully active when the device enters a low-IQ sleep.

    It's hard to estimate a safe AEF current, you can use the VCC capacitance and AEF current with the capacitor equation I = C* dV/dt to estimate the time for VCC voltage to drop a certain amount to VCC UVLO, but estimating the time in sleep is a bit harder. I think you can use the capacitor equation again with the output capacitance and output current, but the output voltage after pulses in PFM is not as controlled so the dV will be a bit harder to estimate.

    Otherwise using a VCCX or in FPWM mode should prevent a VCC UVLO.

    Hope this helps,

    -Orlando

  • 0 in reply to Orlando Murray
    Intellectual 410 points

    Hi Orlando,

    thank you for detailed answer. I think this answers all my questions for now.