Hi Team,
My customer uses UCC24612-2 for SR MOSFET control in PFC cirucit, and he finds a short period of VGS overlaping under CCM, just as the pictures show below.
Will this be a risk of shot-through on high/low side MOSFETs? Is it possbile to add some dead time between SR FET turn-off and main MOSFET turn-on?
CH1: PFC main MOSFET VGS
CH2: SR MOSFET VGS