• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 61 subscribers
  • Views 530 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS61288: Phase compensation design

TPS61288: compensation

Damiano Cosma Potenza
Prodigy 50 points
Part Number: TPS61288


Hello,

I am designing a board based on the TPS61288 boost converter.
In my application I have a VIN (6V to 8.4V, 2S Li-ion battery), VOUT 13V and IOUT max 3.5A.

I calculated the values of the following components, making calculations based on the formulas in the datasheet:
R1 = 274 kΩ
R2 = 13.3 kΩ
L = 2.2 µH
Coutput = 114 µF (22+22+22+47+1)
Cinput = 69 µF (22+47)

I am trying to calculate the value of the components Rc, Cc, Cp for the phase compensation, using the equations 12, 13, 14 of the datasheet, but I can not do because I don't have the values of Ro and RESR, and it is hard to find the real values of Couput, Cinput under the various conditions(derating).

So, is the compensation network very sensitive or can I use the same network of evaluation board even if the boundary conditions are different?
I look forward to receiving your feedback.

Thank you!

  • 0
    TI__Expert 4760 points

    Hi Damiano,

    Ro=VOUT/IOUT=13/3.5, RESR can be assumed as several mΩ if you used MLCC. Note that the DC derating of capacitance should be taken into consideration. You can also use the calculation tool and design the parameters at lowest VIN: 

  • 0 in reply to Yichen Xu
    Prodigy 50 points

    Hi Yichen Xu,

    Thank you, we are working on the Design Tool that you had adviced. But :

    1 we don't know how calculate the "effective output capacitance" or "output capacitor ESR", on datasheets do not reports these information. Can you advice me something? (exists typical value, measurment methods,..)

    In attachments there are two files of the Design Tool, one relative to Evaluation Board (the data have been inserted from us) and one relative to our board.

    2 The desidered Bode diagram, is that of original file (that downloaded from the TI website)? The values for compensation net obtained in file_our_board, are ok? 

    3 If the step-up is stable with a determinate current (ex 1A), could be instable to another (ex 300mA)?  

    4 It is possible to have the XLSX file relative to evaluation board? So we have a pratical example of calculation.

    5 There is a document where is explained, how perform bode measurments on evaluation board?

    thank you

    TPS61288 Calculation tool - Our board.xlsxTPS61288 Calculation tool - EVBoard.xlsx

  • 0 in reply to Damiano Cosma Potenza
    TI__Expert 4760 points

    Hi Damiano,

    1. Effective capacitance could be found in datasheet or website of the MLCC you choose. For example, you can find

    in muratahttps://www.murata.com/products/productdetail?partno=GRM32ER71E226KE15%23

    2. Using the calculation tool to design compensation parameters is very effective and applicable.

    3. Yes, you should use minimum Vin and maximum Iout to design, which is the worst case. Other conditions should work fine.

    4. The EVM parameter may not be designed for its worst case so it is hard to make a example.

    5. You can refer this article for measuring: 

    e2e.ti.com/.../power-tips-how-connection-wires-affect-bode-plot-measurements

  • 0 in reply to Yichen Xu
    Prodigy 50 points

    Hi Yichen,

    thank you very much for your replies. I would like to ask you something else.

    1 What happened if the inductor peak to peak current ratio is higher than 40%?
    2 The step up could cause EMC problem? (we have to certificate the system) How avoid them?
    3 On Evaluation board (between the output capacitors) there is C3, an automotive capacitor that is 1uF 50V. What is its function? 
    4 Is there an order to link Cc and Rc to pin COMP? In some schematics the order is Cc, Rc (Cc on pin COMP), in other is Rc,Cc(Rc on pin COMP).
    5 Could you give us a graph of an ideal bode plot to obtain boost stability?

    thank you

  • 0 in reply to Damiano Cosma Potenza
    TI__Expert 4760 points

    Hi Damiano,

    1. If inductance is smaller, the peak current is bigger so you need to choose a higher current rating inductor. And the larger current ripple will bring worse EMI performance.

    2. EMC is a common problem for switching converters. For Boost, you can optimize the layout/add ferrite bead/or choose a boost with dithering feature to optimize the EMI performance.

    3. It is placed next to the IC to bring small switching loop for reducing SW spike.

    4. There is no order.

    5. A good bode plot for Boost should be like this.

     

  • 0 in reply to Yichen Xu
    Prodigy 50 points

    Hi Yichen,

    could you send also a good Bode plot  for Boost also for the phase?

    thanks

  • 0 in reply to Damiano Cosma Potenza
    TI__Expert 4760 points

    Hi Damiano,

    This is an example.