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Hello,
Could you please review the TPS544C20 layout design below?
In particular, please review whether there is no problem with heat dissipation when the power inductor and DCDC IC are stacked top and bottom.
A heatsink will be attached to the power inductor.
Top Bottom Top + Bottom
Thank you.
JH
JH,
The primary path for power dissipation in the TPS544C20 is through the exposed thermal pad into the PCB's ground layer. Unfortunately, ground is not captured in this layout description. Thermally, the inductor has demonstrated to be a good path for a heat sink, generally conducting head away from the IC through SW.
One element of the TPS544C20 layout that is critical that I can't see in the schematic is the kelvin ground connection between AGNDSNS and the AGND pin. I do not see how these are connected. It is important for current sense that AGNDSNS not be connected to PGND and to have a short, wide trace to AGND. Typically TI recommends 2 vias at any layer change.
Additionally it is best if the AVIN pin is bypassed to this AGND to AGNDSNS connection nearer the AGNDSNS end so that the AVIN bypass ground does not induce AGND to AGNDSNS currents.
Hi Peter,
Thanks for your reply.
Could you please provide a clearer guide to the customer's design with the power inductor and DCDC IC stacked Top and Bottom?
Are there any cases where this design has been accepted and applied?
Please refer to the attached PCB designs below.
Thank you.
JH
JH Shin,
Here is a TPS544C20 Reference Design using the stilted inductor "Inductor on Top" design - https://www.ti.com/tool/PMP10364
The TPSM846C23 and TPSM846C24 modules also use stilled inductor "inductor on top" design
https://www.ti.com/product/TPSM846C23
https://www.ti.com/product/TPSM846C24
We have also had a number of customers implement inductor on top designs using the TPS544C20, TPS546C23, and TPS549D22 all in the same 5mm x 7mm QFN package as the TPS544C20.
My primary concern with your layout that you shared is that the GND_DCDC1 ground appears to be a separate net from the main PCB ground, which leaves me to believe that GND_DCDC1 may only be present on the layers shown. That concerns me that there is insufficient ground available for thermal spreading of the heat generated inside the TPS544C20 or for carrying the high dI/dt switching currents and DC ground currents of the converter.
Is there a reason for isolating the ground of the TPS544C20 from the main system ground? How is the ground of the TPS544C20 converter connected to the system ground?