Other Parts Discussed in Thread: OPA2374
On the startup timing, /FLT output assert Low (probably UVLO) and not release to High in spite of /SHDN Low ⇒High.
Please let me know about two points below;
・Timing or the other condition for Latch to restart (/FLT to high)
・If below connection wrong or any advice for fault output condition, please let me know.
【Information】
・Connection diagram is attached below.
Timing delay circuit is based on OPAMP(OPA2374), in order to make time lag for /FLT output reset after +12V startup.
・Waveform is attached below, please ignore ch4 waveform.
・About /SHDN time for High ⇒ Low ⇒ High; when Low term set too long: 0.5sec and 1sec, /FLT is also keep Low.
・When change to TPS26602 (auto retry), /FLT output become high for after startup.
But one customer need to use latch function of TPS26601.
We hope to solve on TPS26601.
Best regards,
Satoshi