TPS543C20: Capability of handling high transient current

Vyshnav vk 

The TPS543C20's current limit and current handling capabilities are limited by its switches and current limit functions.  A load current pulse of 1-10ns will be handled by the output capacitors and will not propagate back through the inductor to the TPS543C20's power FETs.  Supporting load current transients on time scales less than a few microseconds depends entirely on the ESR and ESL of the output capacitors and their PCB layout.  The converter and inductor will support these very fast load transients averaged over the time constant of the converter's closed loop bandwidth.

Vyshnav vk said:

1. In this case whether IC will be able to handle such high transients.?

The TPS543C20 includes a 60A (typical) high-side FET current limit which will truncate the switch current with a peak of 60A, delivering a maximum inductor current less than 60A to the output capacitors.  Load currents greater than this high-side FET current limit will be handled by the output capacitors, decreasing VOUT.  In addition, the TPS543C20 implements a low-side current limit.  The low-side current limit extends the off-time, limiting the valley current of the inductor.  This can limit the output current to less than 60A depending on the ILIM setting

If VOUT drops below the Power Good lower threshold (falling), PGOOD will assert low.

If VOUT drops below the Under Voltage Protection threshold (falling) the converter will shut-down, time out, and then restart (Hiccup)

Vyshnav vk said:

2. What is maximum transient that the IC can handle ( 2 Phase stacked configuration ) ?. As per one of our earlier discussion its been told that 120A can be handled by stacked 2-Phase configuration ( 60A each ). In this case what is the maximum pulse width/the transient time with 120A that IC can withstand.

The converter can sustain 60A load current for an extended period of time, but operation in circuit will depend on the value of Cout and how far above the current limit the transient current is, as excess current will decrease VOUT and trigger Under Voltage Protection.

Vyshnav vk said:

3. If TPS543C20RVFT IC is unable to handle such high transient currents, then what will happen for the IC if such high transient is been introduced by load. Will it go to over current protection state and blank out or IC will go bad. 

The High-side and Low-side current limits will clap the switch current, leaving the output capacitors to deliver the differential current until Under Voltage Protection triggers a shutdown.

Vyshnav vk said:

4. How much minimum decoupling capacitance should be provided on the board to handle such high surge currents in VRM. Please provide your input for the same.

A 10ns pulse at 150A contains 1.5μC of charge.  The amount of output decoupling capacitance needed to support such a transient depends on the output voltage deflection needed to maintain during that 10ns.  Due to the high dI/dt, that output capacitance will likely need to be made with a large number of small ceramic bypass capacitors very close to the loading IC, and will depend on the voltage deflection allowed.  150μF with virtually no ESR or ESL due to being made from a large number of smaller capacitors, would discharge 10mV during that 10ns.

Additional larger ceramic capacitors and bulk capacitors will likely be needed to support the average transient to the bandwidth of the converter as well, but the amount needed depends heavily on the Switching Frequency, Inductor Value, and the change in time-averaged load current.

1) What is the minimum time-averaged loading current seen by the converter averaged over 3 switching cycles?

2) What is the maximum time-averaged loading current seen by the converter averaged over 3 switching cycles?

3) What is the allowed output voltage deflection (change in Vout) in response to the transition between these two states?

4) The peak output impedance of the converter must be equal to or less than ΔVout / ΔIout

5) The output capacitors will need to provide that output impedance, or less, at the closed loop bandwidth of the converter.  For switching frequencies up to 500kHz, 1/5 the switching frequency is generally obtainable.  For switching frequencies above 500kHz, the bandwidth beyond 100kHz is typically reduced by about 2kHz for each 100kHz past 500kHz due to additional loop parasitics above 100kHz.  (@ fsw = 600kHz, 118kHz bandwidth, @ 700kHz, 134kHz bandwidth, etc)  These are estimates of the approximate bandwidth that will be achievable for sizing output capacitance.  Layout and component selection can affect the loop capabilities.

To calculate the output impedance of a capacitor at a given frequency, use the formula ESR + 1/ (2*pi*f*C) for each capacitor and then consider Zout of all of the capacitors in parallel.  Zout(total) = 1 / ( 1/Zout1 + 1/Zout2 + 1 / Zout3...)

Vyshnav vk 

In the future, when asking a new question not related to the original question and thread title, please create a new question.  That helps other engineers search for and find the answers to the questions more easily.

However:

Yes, the TPS543C20 can work with the LM10011 current DAC to provide parallel VID for dynamic voltage change, static voltage scaling, or margin testing.

Since the LM10011 can only source current, no sink capability, you will need to see up the TPS543C20 to generate the highest desired output voltage when the LM10011 is sourcing no current and the lowest desired voltage when the LM10011 is sourcing the most current.

For 0.8V +/- 15% (0.68V - 0.92V) Leave the VSEL selection at 0.8V and add an external divider between VOUT, RSP and RSN to raise VOUT to 0.92V when the LM10011 is not sourcing the lowest amount of current.

Size the top resistor (VOUT to RSP) for 120mV of drop with the DAC current difference between the MSB (Code 1000) and MSB -1 (Code 0100) of the DAC is enabled (15μA)  (120mV / 15μA = 8kΩ.  The closest standard resistor is 8.06kΩ

Size the bottom resistor for 0.92V when VRSP = Vref = 0.8V and IDAC = MSB = 1 (Code 1000, 26.4μA)

(Rbot = Vref / [ ((Vout - Vfb) / Rtop + Idac @ 1000 ] = 0.8V / [ (0.92V - 0.8V) / 8.06kΩ - 26.4μA ] = 0.8V / (14.88μA + 26.4μA) = 19.38kΩ

Closest standard value is 19.1kΩ

Set LM10011 to 4-bit mode by pulling the MODE pin to VDD

To select 0.92V, Release Bit 3 only (VIDS = 1, Code 1000)

To select 0.8V, release Bit 2 only (VIDC = 1, Code 0100)

To select 0.68V, hold all VID pins low (Code 0000) 

The LSB adjustment resolution of the 4-bit DAC is 30mV.

This provides simple, single bit VID transitions between 0.68V, 0.8V, and 0.92V for margining, but does not make full use of the resolution capabilities of the LM10011.  If you need better resolution between 0.68V and 0.92V, we can adjust the resistor values to make use of the full scale capabilities of the LM10011. 

Vyshnav vk  

My apologies for using the incorrect pin label.  That should be the RSP pin not the FB pin.

The TPS543C20 can be used with a resistor divider to select a voltage other than the reference listed in table 8.4.4 using the circuit described in Figure 22, Section 8.4.16.

Rtop is placed between Vout and RSP and Rbot is placed between RSP and RSN.

The LM10011 current is then sourced into the RSP node.

I will edit the prior response to correct the FB / RSP pin label.  Again, my apologies for that.

Vyshnav vk 

The TPS543C20 regulates the output voltage by driving the RSP - RSN = VREF, where VREF is set by the VSEL resistor.

When there is no resistor between VOUT and RSP and no resistor from RSP to RSN, then RSP will be equal to VOUT, and VOUT will be regulated to the VREF voltage selected by the VSEL resistor.

When there is a resistor between VOUT and RSP and a resistor from RSP to RSN, the TPS543C20 will continue to regulated the voltage at the RSP pin equal to the reference voltage selected by the VSEL resistor, but the output voltage will be a scaled version of that voltage.

For example, if the VOUT to RSP resistor = RSP to RSN resistor, the RSP voltage will be 1/2 the VOUT voltage and VOUT will be regulated to 2x VREF when RSP = VREF.

My above calculations are based on VREF = 0.8V, so:

VSEL still needs to be terminated to GND to select VREF = 0.8V (23.7kΩ to GND)  Floating the VSEL pin would result in VREF = 1.0V, which would require a different resistor divider and different VID codes to select the desired 0.68V, 0.8V, and 0.92V options.

The RSP voltage will be 0.8V

Vyshnav vk 

Refer to the reference schematic for a two-phase application section 9.3.1 - Figure 32

RSP and RSN are only connected to VOUT for the primary device (master) of the stack.

VSEL is terminated with a resistor on only the primary device.

The secondary device does not need VSEL programming since it's voltage loop is bypassed and the current control loop is run by the primary device.

VSEL, RSP, and RSN can be shorted to ground.

Vyshnav vk 

For 20mV resolution, you will need to select different resistors than the ones I posted above, but 20mV steps are within the resolution of the LM10011 using the TPS543C20, though the codes to select 0.68, 0.80 and 0.92 will be a little more complicated.

For 20mV resolution with the 3.76μA LSB of the LM10011, you'll want a top resistor of 5.36kΩ

You can then size the bottom resistor to select 0.8V at mid-scale (1000) to allow 140mV up positive adjustment and 160mV of negative adjustment.

Code 8 (RSET = 140kΩ) has a current of 26.4μA.  To set VOUT = 0.8V with a 0.8V reference, the bottom resistor will need to be 30.1kΩ.

Vyshnav vk

You said that you wanted to cover the range of 0.68 to 0.92 with a nominal value of 0.80V and a step of 20mV.  Rather than set the 0A (Code b'1111) value to 0.92V, I set the mid-scale (Code b'1000) to 0.8V.  That allows for a range of 0.62V to 0.94V.  If you set 0.92V at the current current level, with 20mV steps, the adjustable range would be 0.60V to 0.92V.  It's really where you want to set the extra 60mV of adjustable, whether you want to split it between positive and negative, or you want to bias it to one side or the other.  If you want to set the range for 0.60V to 0.92V, size the resistor divider for 0.8V when CODE b'1001 is selected (Rset = 154kΩ, Idac = 22.6μA, which calculates to 35.4kΩ, the closest standard value being 35.7kΩ)

You want to set the divider based on the target nominal voltage, not one of the end points because it's the nominal voltage you want to be most accurate.

Vyshnav vk 

The LM10011 will make adjustments to the regulation target of the TPS543C20, so the two loops wont be fighting, but the best option would be to set the sense point for the resistor divider to RSP to the point you want regulated.  The LM10011 will have 20mV resolution, so it's not going to be able to make fine output voltage to adjust to cancel small drops across the current sense resistor.

With the top resistor of the RSP to RSN divider connected to Vout after the current sense resistor, the analog loop should cancel the drop across the current sense resistor.