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Hello TI experts,
My customer wants to review the layout for their new product. could you help me?
first of all SNVA729A document, there are some descriptions about LMG5200 power stage layout.
they worried about this layout because they could not use vias to connect PGND from LM5200 to VIN capacitors, just place capacitors between PGND and VIN.
(you can understand it if you see the layout.)
we have to check that there are any "significant overshoot on the switch node" or other serious side effect.
i attach a pptx file for your convenience.
Best regards,
Chase
Hi Chase,
It is recommended to have vertical power loop connection (return path from bypass capacitors directly underneath the top layer) to optimize the power loop inductance. In the attached layout, it looks like there is a lateral power loop which typically introduced higher parasitic inductance. From the attached file, I do see enough space to implement return path on layer 2, if capacitor is placed directly above the GAN.
Yes, the major side effect you will see as a higher overshoot voltage.
With Regards,
Prasanna