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UCD3138A64: How to implement phase shift between DPWMs?

Part Number: UCD3138A64

I'm trying to implement a dual active bridge controller with the UCD3138A64.  I'm starting simple with a DPWM0 and 1 driving the primary side FETs with 50% duty cycle (a little less with dead time) and DPWM2 and 3 driving the secondary side FETs with 50% duty cycle and want to use the phase shift between 0/1 and 2/3 to control the power flow.

Unfortunately from what I have pieced together in the register guides, app notes and these help forums is the A64 version has removed the capability to set the PHASE_TRIGGER from a filter output.  I'm trying to figure out if there is a work around to achieve this same effect in hardware with the available filter outputs. 

I tried implementing an IRQ routine to have code check the front end error output and adjust the phase shift accordingly, but found that took ~3.4us.  Does that seem reasonable?  (I'm a HW eng not a FW eng so I don't have a good frame of reference, but that seems like a lot of clock cycles for a simple task.  Maybe there is some much better optimization that can be done there?)

I'm using a 1MHz switching frequency and would ideally like my primary control loop operating at the same frequency.  Even if the IRQ service time could be reduced to fit in this time, it still seems like it will use up way too much of the processor capability, so a solution in HW seems better.  It appears most or all of the filter outputs are designed for controlling duty cycle rather than phase shift.  Is there some way this could be adapted to achieve the phase shift I need?  Something like use the filter to set a DPWMC duty cycle and use a DPWMC edge to create trigger the start of the secondary cycles?    

  • We've implemented what you're looking for in the PSFB EVM here:

    It uses the edge generation hardware, and it can be done using either PCM or voltage control.  We developed this method to support PCM, and it also worked for voltage mode, so we took out the filter controlled phase shift.  It's very complicated, so you really need to use the EVM code as an example.  It would be a long road to reinvent it.  

  • Thanks for the feedback- I looked through that code previously and for some reason thought it couldn't be adapted to what I need to do for the DAB, though the exact reason escapes my memory.  I'll give it another go.

  • Hello Ian- is there a version of this code for voltage control or average current or a description of how it operates?  I'm struggling to put together a coherent picture of how this code is supposed to work and how it relates to what I am trying to do. 


    From what I have pieced together in the PCM code, the filter output is fed back to the front end DAC setting which is used to adjust the pulse width in hardware.  I have not been able to figure out how/where an adjustable phase shift between DPWM2 and 3 is introduced. 



  • If you want to friend me on the forum and send an email, I can send you some notes that will help a lot to understand it.  They're not really ready for prime time, but they should be very helpful.  Basically the PCM mode has a complex use of edge generation logic to make a phase shifted full bridge using fixed outputs on the DPWMs which are cut short by the peak current event.  To convert it to voltage mode, you use exactly the same DPWM setup except you control the timing of the DPWMs with the filter output rather than the peak current event.   

  • I've sent out the notes, and I'm going to close this thread.