TPS6521855: WAIT_PWR_EN/termination of unused pins

Hi Shota,

1) Your understanding is correct. When the device reaches WAIT_PWR_EN the rails should activate again, assuming the fault has been fixed. As long as you have PGOOD asserted high at this point, a high PWR_EN will allow you to move back to ACTIVE state.

2) For pin terminations:

• PB should still be tied to IN_BIAS through 100k pull-up resistor so that no reset signal is seen from this pin during operation
• nWAKEUP is not involved in any state transitions so I believe it can be left floating if not connected to SoC
• nINT is also not involved in any state transitions. I think you can leave this pin floating. Interrupts can be masked for extra security.
• GPIO2 and GPIO3 can be left floating
• IN_LSx and LSx pins can be left floating since they are not included in the voltage monitoring
• PFI and nPFO pins can be left floating. Make sure that the OFFnPFO bit in the CONTROL register is set to "0" so that the power fail comparator doesn't control the power down sequence (see Section 7.3.1.9 of the datasheet for more information).

If you have any issues with these pins or the power sequence let us know here on E2E.

Regards,

James

Hi Shota,

That is correct. If PWR_EN is high the device will automatically move from WAIT_PWR_EN to ACTIVE state.

Regards,

James