UCC28061: Gate waveforms working at different frequencies and duty cycles

Hi Ernest,

This is likely an issue with the quality of the ZCDx signals which are used by the PLL to control the synchronization of the phases. Perhaps if you include those signals along with the GDx signals we can see what's happening. 

At what load do the GDx sync out of phase?

This issue may be related to component placement/layout. Please verify that layout guidance in on page 23 was followed https://www.ti.com/lit/ds/symlink/ucc28061.pdf

Specifically:

• Verify the caps on ZCDx are close to the device pins and connected directly to AGND.
• Verify that RTSET is close to the device pin and connected directly to AGND.
• Verify that the drains of the MOSFETs connect to PGND plane

Regards,

Ray

Hi Ray,

Thanks for your detailed feedback. I see some improvements on the high voltage lines. But on the low line it's the same... The waveforms attached is for your reference: 

In addition, could you also help to us to understand the IC Operation:

1. Why do the two gate outputs work at different frequencies?
2. Why are the two gates not running 180° out of phase.
3. Why are the two gates always turn on at the same time during start up?

Thanks.

Hi Ernest,

I'm glad to hear you have improvements. You didn't share what you did to get those improvements nor what the actual issue is.

1. Your waveforms are difficult to read details, but in the lower one I see twenty pulses for each gate, so they are the same frequency. It's not easy to see, but the first waveform also appears to show the same number of pulses.

2. By design, the two gates always turn on in-phase: during startup, after an OC event, when PHB is re-enabled after a transition from single phase to dual phase (interleaved) operation, and when there is a loss of a ZCD signal. After one of these events, the PLL will slide the outputs out of phase by 180° (this usually occurs within several cycles). I can see that happening in the zoom on the first waveform and also on the second waveform, so from what I can see, it appears to be operating as expected.

3. This is by design. See #2.

In general the two outputs won't necessarily match with phase and duty cycle if there is a fault or if the system is unstable.

I don't see a misbehavior with the last two waveforms you provided (although I can't clearly see the first of the two). Is there a regulation issue? 

Regards,

Ray

Hi Ray,

The improvement is from connecting CZCDA and CZCDB directly to AGND. But this improvement is only reflected in the high voltage lines.

Hi Ray,

Thank you for your help so far, customer is facing improvements with your suggestions.

They have requested for some direct email support from our product team for this device. May I kindly loop you into the email with my customer?

Thanks again for your great help!

Hi Ernest,

I just sent you an email response.

Ray