Other Parts Discussed in Thread: UCD90320, , PCA9517
Hi Team,
My customer is seeing an issue with i2c access to the UCD90320U. They are using this on a lot of boards, and have noticed that on boards with the UCD90320 behind an i2c buffer like the PCA9517A, we tend to see lots of PEC errors, and even bus hangs. We can clock a few cycles on the i2c clock and the situation will clear, so it seems the UCD90320 is missing some clock cycles at some point and is stuck in a transaction and holding the bus low.
I don't know how familiar you are with devices like the PCA9517, but they implement an offset on logic "0" on the secondary side of the bus that is offset by 500mV above ground so that it can tell the directionality of who is driving (if buffer is driving low from primary to secondary, output is 500mV, but if device on secondary bus is driving it goes to 0). I can tell the UCD90320 is holding the bus low since the SDA line is ~0mV.
The only V_IL spec I see in the datasheet is for 0.35 * V33D which would be > 1.1V, which we meet in all cases. The max I've seen is ~550mV on the board that is consistently failing. Although the datasheet specifically calls out pins like GPIO, Logic GPO, EN and Margin Pins but not PMBUS_CLK or PMBUS_DATA.
- Can you confirm the V_IL spec on PMBUS_CLK and PMBUS_DATA pins?
- Are you aware of any similar issues with other customers having i2c / pmbus comm troubles with this part?
- We also noticed in early integration that after a page write to offset 0x00, we needed to add a delay to subsequent transactions like read_vout or else we would see errors. I did not see any timing spec in the datasheet, so would be good to confirm if there is a timing spec after a page change, or perhaps this is related to the initial issue.
-Mitchell
