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TPS7H5001-SP: Maximum voltage on COMP pin

Part Number: TPS7H5001-SP

Table 7.1 Absolute Maximum Ratings in the data sheet SLVSF07A specifies that the maximum voltage is 3.3V, yet the PSPICE simulation provided in slvmdq0.zip produces a peak voltage of 5V at the COMP pin shortly after the output voltage is shorted in the simulation.  Is that realistic?

What is the highest voltage that the COMP pin can deliver due to the error amplifier?  Also what is the minimum output voltage from the error amplifier at the COMP pin?

Also, the provided PSpice model is very slow.  It takes several hours to run on a fast computer with 8 Xeon cores and 256 GB of RAM.  This is with the latestFlyback Simulation.pdf version of PSpice A/D 17.4.

  • Hi,

    We will answer your questions when we return to the office Monday.

    Thanks

    Christian

  • Thanks, Christian.

    I removed the shorting switches to see how the converter operates.  I found that the duty cycle is unstable and looks like subharmonic oscillation, but it might be something else because I couldn't make it stable even with a slope compensation resistor as low as 100k.  It would be helpful if the data sheet section 8.3.17 Slope Compensation explained how to select the resistance for flyback converters.

  • Hey Bryce,

    The max comp voltage of the model is not the same as the actual device.
    This is a known issue that needs to get fixed.
    You can expect the highest COMP voltage in reality to be 3.3 V.

    Note that this is not the useable range of the COMP voltage as an input.
    COMP should vary between ~0 V and ~2 V during normal operation.
    This is due to the COMP voltage being compared to the CS_ILIM pin.

    If you are looking for how to do slope compensation for flyback converters, we both have a calculator on the TPS7H5001-SP page for flyback converters as well as a program to help you called Power Stage Designer here:
    https://www.ti.com/tool/POWERSTAGE-DESIGNER

    Thanks,
    Daniel

  • I was never able to get the PSpice simulation to avoid the subharmonic oscillations, so I decided to try the Simplis model.  Adjusting Rsc in the Simplis model works.  However, I expected to see the voltage at COMP to be about twice the peak values at CS_ILIM because CCSR is supposed to be approximately 2.  Instead, the voltage at COMP is about three times higher than the peak values at CS_ILIM.  I thought this might be related to the value of Rsc, but it isn't.  I found this is true for both the slvmdm7 Push-Pull and slvmdp9 Flyback simulations. In other words, the simulations seem to behave as though CCSR is three instead of two.

  • Hey Bryce,

    Double checking I dont see the same 3x you are seeing.
    I dont see 2x, but RSC should change the COMP voltage internal compared to the CS_ILIM pin.
    This is because the COMP voltage is subtracted from then compared to the CS_ILIM pin

    What RSC values did you check when looking for changes?

    Thanks,
    Daniel

  • I made a mistake when I said that the ratio doesn't depend on Rsc.  I re-ran the simulations and found that the ratio varies but is still closer to 3 than 2.

    For example, in the slvmdp9 Flyback simulation, Rsc has a value of 540k when the simulation is unzipped.   At steady state, ~20ms, when:

    RSC=540k, COMP=1.125, CS_ILIM=0.395, Ratio=2.85

    RES=700k, COMP=1.11, CS_ILIM=0.395, Ratio=2.81

    RES=1MEG, COMP=1.10, CS_ILIM=0.395, Ratio=2.78

    RES=2MEG, COMP=1.10, CS_ILIM=0.399, Ratio=2.78   (Subharmonic oscillations)

    So, with minimal slope compensation, the ratio is 2.78.

    For my own flyback simulation with lower duty cycles in which DCL is grounded:

    RSC=540k, COMP=1.44, CS_ILIM=0.448, Ratio=3.21

    RSC=5.4MEG, COMP=1.18, CS_ILIM=0.448, Ratio=2.63

    RSC=54MEG, COMP=1.17, CS_ILIM=0.448, Ratio=2.61

    So, with essentially no slope compensation the ratio is 2.61

  • Hey Bryce,

    I have found the issue that you are running into.
    There is a 150 mV offset between the CS_ILIM pin and what is actually being put into the comparator.
    This makes the equations make some sense as running one of the examples quickly CS_ILIM = 0.399 +0.15 = 0.549 -> 0.549 *2 = 1.098 which is a rounding error from 1.1.

    I'm confirming that the 0.15 V offset is in the real device too, but I suspect there is in fact a 0.15 V offset in CS_ILIM to the comparator.

    Thanks,
    Daniel

  • Hey Bryce,

    I have confirmed with the original designer that the 0.15 V offset is included in the real part.

    Thanks,
    Daniel

  • Will the datasheet be updated to reflect this offset? Seems like an important detail esp. for designs that need to sometimes operate at light load!

  • Hey Brian,

    I will work internally to see if we can get this added to the datasheet.

    Thanks,
    Daniel