We are using UCD9090-Q1 device in our system. The connection involves enabling voltage rails and monitoring them. The voltage rails have warning and fault thresholds defined to be +/-10%. All actions on fault are disabled, therefore, faults will only be logged. The voltage rails being enabled, have controlled power up ramps. In ramps are between 3ms to 12ms. Glitch filters for all monitors are disabled. 'Max Turn On' times are set to be infinite.
During powering up, we see occasionally PMBUS_ALERT is asserted. This only happens during power up. Once cleared, the alert never occurs even under extreme load conditions, and correctly so as we are also externally monitoring the rails. The only explanation for PMBUS_ALERT assertion we can hypothesize is that due to slow ramp up, at the point when rail crosses UV threshold, the subsequent ADC sample may read the voltage rail as below UV threshold, and then back above UV threshold. The reason for this could be nonlinearity in ADC, which is defined to be +/-4 LSB.
Does this explanation hold water?
