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UCC5870-Q1: Some of UCC5870-Q1 Question

Part Number: UCC5870-Q1

Hi Expert

we have five question as below:

1. can we choose below way to design the OUTH and OUTL driver resisters?

2. what difference between VCECLP and DESAT?

3. if we needn't AI2~AI6, How to connect it? pie to GND?

4. what function is below R14 and R15? what condition need to post it?

   

5: how to calculate decoupling capacitor in the VREG2 and VEE2? Is it must 4.7uF? customer want to to choose 2.2uf, is ok? 

  • Hello Meng,

    Thanks for your interest in this part. I have attempted to answer your questions below. Please let me know if you need more clarification.

    1. can we choose below way to design the OUTH and OUTL driver resisters?

    While this configuration should not cause problems for the device, I question why it is desired. Generally, this configuration is used with a driver that only has a single output and allow the designer to select different turn on and turn off resistance. However, since the UCC5870 already has separate outputs for turn on and turn off I don't see any benefit of this configuration, and there is added cost due to the extra diode.

    2. what difference between VCECLP and DESAT?

    The DESAT pin is a protection mechanism to allow immediate turnoff of the power switch if the drain source voltage is too high, indicating a short circuit or over current event. This protection is active when the power switch is on. The VCECLP pin protects from a voltage spike above the power switch Abs Max, generally when the power switch is off. (See datasheet section 7.3.5.7)

    3. if we needn't AI2~AI6, How to connect it? pie to GND?

    These pins should be pulled to GND if they are not in use

    4. what function is below R14 and R15? what condition need to post it?

    These resistors are not necessary if the AI4 pin is not in use. R14 would be used if the customer wanted to monitor the DESAT voltage with the AI4 channel. I am not immediately sure the purpose of R15 and would have to check if the customer is curious. In general terms, its purpose would be to condition the signals on the AI4 input to ber within the required thresholds.

    5: how to calculate decoupling capacitor in the VREG2 and VEE2? Is it must 4.7uF? customer want to to choose 2.2uf, is ok? 

    We recommend a 4.7uF capacitor in parallel with a 100nF capacitor as close to the device as possible. 

    Please let me know if you have any follow up questions, or if this answers your questions. 

    Regards,

    Daniel