• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 456 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3840: timing diagram

Kai Nomiyama
Expert 5615 points
Other Parts Discussed in Thread: TPS3840

Hi Team,

I have a question about TPS3840 /RESET timing diagram.
regarding start up timing, I described two cases in attached figure but could you check these are expected behavior?


- tSTRT incules tD(no cap) so actual internal activate timing should be tSTRT - tD(no cap) = 320us_max.
- tSTRT starting point is VDD(min) crossing point.


Case 1: tSTRT > tVDD_VIT+ (VDD can ramp up to VIT+ within tSTRT time)
in this case, VDD can ramp up to VIT+ within tSTRT time so /RESET asserts after tSTRT(the start point is VDD(min)).
tSTRT incules tD(no cap) so if there is CT cap, total timing is tSTRT + tD(ct).


Case 2: tSTRT < tVDD_VIT+ (VDD cannot ramp up to VIT+ within tSTRT time)
in this case, tSTRT starts from VDD(min) and /RESET keeps low untill VDD exceeds VIT+.
Once VDD exceeds VIT+, /RESET asserts after tD(the start point is VIT+).
total timing is tSTRT - tD(no cap) + twait + tD.

Regards,

Kai

TPS3840 timing diagram.pptx

  • 0
    TI__Genius 9170 points

    Hello Kai, 

    I am reviewing your diagram. I will provide an update by tomorrow 9/14/22 2:00 PM PT. 

    Regards, 

    Oscar Ambriz

  • 0 in reply to Oscar Ambriz
    TI__Expert 5615 points

    Hi Oscar,

    sure, thank you for your help.

    Regards,

    Kai

  • 0 in reply to Kai Nomiyama
    TI__Genius 9170 points

    Hello,

    - Correct. When VDD starts from less than the specified minimum VDD and then exceeds VIT-, reset is release after the startup delay (tSTRT), a capacitor at CT pin will add tD delay to tSTRT time

    - At start up the "startup delay" will begin after the Vpor voltage is has been reached.

    Slide Two

    Case 1: I believe the starting point of the "start up delay" should be moved to after the VPOR has been reached. 

    Case 2: The tD delay associated with the first time VDD crosses VIT+ should begin after the VIT+ crossing point not when it has reached its final value. I believe the correct behavior for case 2 is shown in slide 3. 

    Slide Three

    Only edit I see is moving the starting point of the "start up delay" to after the VPOR voltage has been reached. 

  • 0 in reply to Oscar Ambriz
    TI__Expert 5615 points

    Hi Oscar,

    could you let me know where I can find below your description in datasheet?
    "At start up the "startup delay" will begin after the Vpor voltage is has been reached.".

    Since below e2e mentioned "tstrt is defined from the point where VDD crosses VDD min level" and figure shows tSTRT starts after the VDD(MIN) is has been reached.
    e2e.ti.com/.../3715128

    I updated attached slide based on your comment so could you review?
    Slide 1: Case1_1 - moving the starting point of the "start up delay" to after the VPOR voltage has been. tSTRT inculdes tD so I don't add tD to tSTRT.
    delay --> tSTRT
    Slide 2: Case1_2 - moving the starting point of the "start up delay" to after the VPOR voltage has been. tSTART doesn't inculde tD(CT) so I add tD(CT) to tSTRT.
    delay --> tSTRT + tD(CT)
    Slide 3: Case2_1 - moving the starting point of the "start up delay" to after the VPOR voltage has been.
    delay --> tSTRT + twait + tD(no_cap)
    Slide 4: Case2_2 - moving the starting point of the "start up delay" to after the VPOR voltage has been.
    delay --> tSTRT + twait + tD(CT)

    Regards,
    Kai

    TPS3840 timing diagram_0915.pptx

  • 0 in reply to Kai Nomiyama
    TI__Genius 9170 points

    Hello Kai, 

    I would like to verify my understanding of the timing diagram with other members of the team. I will return with an update by tomorrow 9/16/22 3:00 PM PT. We appreciate your patience. 

    Regards,

    Oscar Ambriz

  • +1 in reply to Oscar Ambriz
    TI__Genius 9170 points

    Hello Kai, 

    I spoke with other members of our team and they confirmed the E2E post you mentioned previously is in fact correct. The tSTRT starting point is the VDD(min) crossing point. I made the edit to your previous file submission. 

    I apologize for the confusion from my end. Thank you for your patience regarding this matter.

    Regards, 

    Oscar Ambriz

    TPS3840 timing diagram_Edit_E2E.pptx