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BQ78350-R2-DEVICE-FW: BQ78350-R2 : SOC calibration mismatch issue

Jitun Mishra
Prodigy 40 points

Part Number: BQ78350-R2-DEVICE-FW

Hello,
We are using BQ79350-R1 IC with R2 firmware as Fuel Gauge to calculate our SOC. As suggested by the Guide for BQ78350, we have used GPC tool to calculate the cell model parameters to be included for CEDV SOC estimation. We have used the parameters as attached below:
"
GPC CEDV tool, rev=60        
Configuration used in present fit        
NumCellSeries=14        
CellTermV=2500        
ChemType=6        
VoltageColumn=1        
CurrentColumn=2        
TemperatureColumn=4        
ElapsedTimeColumn=0        
FitMaxSOC%=13        
FitMinSOC%=6        
LearnSOC%=7        
        
CEDV parameters resulting from the fit. If EDVV bit is set to 1, EMF and EDVR0 have to be multiplied by the number of serial cells when written to data flash        
        
EMF    3590    
EDVC0    441    
EDVC1    0    
EDVR1    19545    
EDVR0    2    
EDVT0    4490    
EDVTC    11    
VOC75    54123    
VOC50    51286    
VOC25    49760    
        
        
Recommended SOC deviation tolerance at EDV2 point is  < 5% for low temperature and <3% for room and high temperature        
        
Deviations for this set of parameters are given below for each file        
        
file    SOC error, %    pass
roomtemp_lowrate.csv    0.847619419798351    1
roomtemp_highrate.csv    -0.580410399569759    1
hightemp_lowrate.csv    1.00351848369134    1
hightemp_highrate.csv    0.432067899070946    1
lowtemp_lowrate.csv    0.0564465851132825    1
lowtemp_highrate.csv    0.126921357288531    1
        
Deviations are within recomended range. CEDV parameters are suitable for programming the gauge
"
We have selected the CHEM ID as per our cell. I have also attached the .gg file that we are using.
We have seen the RSOC dropping from around 28% to 7%(Battery low%) even when the 'Fixed_EDV2' parameter is not reached(2.9V, the lowest cell voltage is seen to be around 3.3V) as well as we have set 'EDV_CMP' as 1 and 'FIXED_EDV0' as 0. Similarly we have seen the battery being shown as charged at around RSOC 85% when the battery is completely charged till cell voltages are around 4.15V.
Also, the 'learned FCC' parameter as well as 'DOD at EDV2' parameter are supposed to be updated after multiple qualified discharged cycles specified by 'requested learning cycle count' parameter, but we have not seen it update correctly even after trying the 'number of learning cycles' parameter values from 2 to 20. Kindly explain this concept as well.
The ASOC value has also been showing lower than the RSOC value and we have also been able to discharge well after the RSOC and ASOC value has reached 0 since there is still charge left.
We are suspecting this may be due to us keeping the 'Design Capacity' parameter as 71.8Ah(according to the cell datasheet) when we calculated the GPCCEDV parameters for an actual capacity of around 67Ah and the true usable capacity we are getting while pack learning is around 60Ah which we have set in order to get better aging.
Kindly check the .gg file attached and let us know if there are anything we are doing incorrectly.
Regards
Jitun
  • 0
    TI__Guru 57697 points

    Hello Jitun,

    Is the load a constant current load or a pulsed load?

  • 0
    Prodigy 40 points

    Hello Shirish,

    The currents used for log files for estimating CEDV parameters is continuous current/constant current load. However, our application is a pulsed load. We also tried re-learning of the pack using constant load first before subjecting it to our application by clearing the cycle counts, however, saw the same results. Kindly let us know where we are going wrong.

    Thank you. Regards,

    Jitun

  • 0 in reply to Jitun Mishra
    TI__Guru 57697 points

    Hello Jitun,

    The constant load is correct method for estimating CEDV parameters.

    One thing to watch out for in pulsed loads is the peak current load. If the peak current load drops voltage to level of the knee voltage, then RSOC will be adjusted by the gauge immediately since the next pulse cannot be sustained by the battery without dropping the voltage below terminate voltage.

  • 0 in reply to Shirish
    Prodigy 40 points

    Hello Shirish,

    We are seeing this issue repeat in constant load condition as well. Should the "Battery Low" parameter be set equivalent to knee voltage according to the SOC vs OCV curve or should it be equivalent to the EDV2 voltage value? Kindly advice.

    So as to summarize our concerns, please find them mentioned below:

    1) SOC dropping from around 30%-20% SOC to 7% SOC during both pulsed and constant load conditions. The SOC is dropping to "Battery Low" 7% value even when EDV2 voltage level is not reached.

    2) SOC not crossing 85% even when Battery maximum charging conditions have been met according to Cell datasheet and maximum possible voltage is attained.

    Points of note:

    1) CEDV parameters have been calculated for constant load conditions as per guidelines given by TI.

    2) EDV_CMP is set and FIXED_EDV0 is not set

    3) "Design Capacity" according to Cell datasheet and the value set in fuel gauge comes to 71.8Ah. Capacity from the data collected for CEDV parameters comes to around 67Ah and actual usable capacity in application comes to about 60Ah

    Additional understanding required of following points:

    1) Capacity learning process

    2) Working of EDV compensation

    Support on these points would be highly appreciated. Thank you for your help. Regards,

    Jitun

  • 0 in reply to Jitun Mishra
    TI__Guru 57697 points

    Hello Jitun,

    For the 85% SOC issue i would suggest reviewing the settings and matching with intended behavior using reference TRM section 5.3 Valid Charge Termination

    Setting the CSYNC bit will probably solve the issue but i would be interested in seeing how it impacts the sudden drop during discharge.

  • 0 in reply to Shirish
    Prodigy 40 points

    Hello Shirish,

    We tried matching the parameters according to the TRM section 5.3 however that didn't resolve the issue, a complete re-flash of the BQ78350 did. We believe it to be related to how the capacity learning happened.

    The CSYSC bit is already set as in the shared .gg file.

    However the SOC drop issue is still not resolved. Is this a common phenomenon during the capacity learning phase? How do we control the number of cycles taken for learning to ensure that the learning is accurate in the minimum amount of cycles?

    Kindly let us know.

  • 0 in reply to Jitun Mishra
    TI__Guru* 79043 points

    Hi Jitun,

    If you can share a log file (click 'Start Log' in BQStudio registers screen) it can be very helpful in debugging this type of issue. EDV2 is getting triggered somehow, so it would be good to see the register readings to see why this might be happening. 

    If any of the cell voltage reading reaches the Pending EDV2 voltage (determined by temperature and load current) the SOC will immediately move to 7%. For a pulsed load, this can be common. Setting the EDV2 Hold Time (along with EDV1 Hold Time and EDV0 Hold Time) and the Overload Current parameters accordingly may help. Setting the [VFLT_EN] bit in the CEDV Gauging Configuration register is also good.

    Regards,

    Matt