Hi team,
According to datasheet, the max SCLK frequency is 400k(fast mode), if we assumed that duty cycle is 50%, then the min SCLK high/low time should be 1/400k*50%=1.25us. However, Min SCLK time is 1.3us for logic low and 0.6us for logic high. These timing requirements conflict with each other.
What is the timing requirement of I2C?
B&R
Lijia
Hi Lijia,
Thank you for reaching out. The I2C timing specification listed in the datasheet is the same as the timing specification listed on official I2C bus documentation from NXP Semiconductor, shown below.
It is possible the specification has simply been rounded up from 1.25 usec to 1.3 usec, but I would also hesitate to assume the SCL signal has a 50% duty cycle.
Best Regards,
Garrett
