UCC28704: UCC28704 Output Issue

Hi Ning,

Thanks for reaching out. Can you provide a waveform of Vout, VDD, Gate(DRV) in one picture?

From the waveform you provided, it seems like FET temporarily stopped switching and therefore output drops. This happens when VDD drops below UVLO threshold (7.7V typical). If VDD is repeatedly dropping and triggering UVLO, increase CDD. (Calculations can be based on UCC28704 excel design calculator)

Can you also provide Naux winding? (Np:Ns:Na)

Thanks in advance.

(UCC28704 datasheet P.27)

Hi Ning,

I discussed with my team and noticed that the series gate resistor is too big (Rg1=5.1ohm).

In the datasheet, it is recommended to have Rg1<1ohm.

Can you also provide a waveform that includes Vout, CS, Gate(DRV) at light load and full load? 

When the FET turns off, the higher series gate resistance makes it more likely that the rise in VDS will cause the FET To turn on again. This kills efficiency and may make the controller believe it is seeing an OC fault.

Dear Claire,

I will send your suggestion to customer.BTW,now we need customer change the Rg1 and provie the waveform that includes Vout, CS, Gate(DRV) at light load and full load.

I want to know if we need customer provide a waveform of Vout, VDD, Gate(DRV) in one picture and the Naux winding? (Np:Ns:Na)？

Thanks

Hi Ning,

Glad to hear that the customer solved the output ripple issue, Other than changing the output cap, did they make any other changes? 

We recommend debugging by looking at the Aux, CS, VDD, Vout together. It is suggested to look at these 4 waveforms and make sure they are in line with the datasheet. If there are further questions, feel free to create E2e thread for support.

Thanks.