This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3702: Several questions

Part Number: TPS3702

Hi all

Would you mind if we ask TPS3702?


<Question1>
The datasheet shows the typical value of tpd(HL) and tpd(LH).
Do you have the mininum value and maximum value of them?
We guess that you do not test this spec in production for every device, you do not guarantee a minimum and maximum value.


<Question2>
The datasheet shows the typical value of Tsd(Startup delay).
Do you have the mininum value and maximum value of this?
We also guess that you do not test this spec in production for every device, you do not guarantee a minimum and maximum value.


<Question3>
There is the description "During the power-on sequence, VDD must be at or above 2 V for at least tSD before the output is in the correct state." on the datasheet.
After VDD is above 2V, during Tsd(typ 300us), what will the status of the output pins OV and UV are? 
It seems that UV is low and OV is high. 
And does "Undifined" mean Hiz?
Is our recognition correct?



<Question4>
Does the any power sequence between VDD and SENSE?
We quess that there is no the any power sequence between VDD and SENSE.
As the background of this question, our customer would like to insert these voltage the same time.

Kind regards,

Hirotaka Matsumoto

  • Hi Matsumoto-san

    1 & 2. The specs that don't have a min and max value generally aren't critical for customer applications, so we don't spec a min and max value.

    3. The Values of UV and OV are active low pins that depend on the input voltage of the sense line. The timing diagram you showed has UV and OV events occur to show how tpd(HL) and tpd(LH) should be interpretted. Undefined means that when the device is turning on and shutting off, those pins could be high or low, and are thus undefined.

    4. Inserting the voltages at the same time should be ok. Besides the 300uS startup delay and having the outputs be active.

    Thanks,

    Andrew

  • Andrew san

    Thank you for your reply.

    In relation to <3.> and <4.>, we would like to confirm followings;

    The situation 1 : VDD = above 2.0V, SENSE voltage = 0V(no Vtarget voltage), within Tsd(300us)
    -> In this case : UV=Low OV=High (UV assert)

    The situation 2 : VDD = above 2.0V, SENSE voltage = Vtarget voltage, within Tsd(300us)
    -> In this case : UV=High OV=High (normal condition)

    Is our recognition correct?

    What we would like to know is the behavior of UV and OV output in case of VDD = above 2.0V within Tsd.
    You mentiond "300uS startup delay and having the outputs be active."
    In case of VDD = above 2.0V within Tsd, regardless of SENSE voltage, are the status of UV and OV Hi-Z?
    Or, do the status of UV and OV output depending on the SENSE voltage?

    Kind regards,

    Hirotaka Matsumoto

  • Hi Masumoto-san,

    Thanks for the question. The OV and UV outputs should actually be active quickly after VDD crosses VPOR (as seen in the waveform). In this case VPOR is 0.8V, and inside devices VPOR is generally defined with ~100mV/uS (to give you an idea of how fast the outputs will move after the VPOR threshold is crossed).

    Thanks,

    Andrew

  • Andrew san

    Thank you for your reply.

    1 & 2. The specs that don't have a min and max value generally aren't critical for customer applications, so we don't spec a min and max value.

    ->Our customer would like to know these data(max and min data of tpd(HL), tpd(LH) and tSD) as the reference.
       (Aproxy like as twice-three times of typ data or more than 10times)
       As the background of this question, the customer concerns that the value will be 100-1000times in case of MIN/MAX. 


    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san

    Unfortunately the min/max values are not a not a published spec and not available.

    Thanks,

    Andrew