Hi,
we are using BQ21062 in our design. We connected VINLS to PMID and LS/LDO to VINLS, as we are not using the LDO capability. Unfortunately, in this configuration there is a high current flowing, which drains the battery, because we somehow missed table 9.2. There seems to be an internal pulldown, if the LDO is not used. As a workaround so far, we put the system into Load Switch configuration and accept a possibly additional current consumption due to the enabled FET. For the next hardware layout we consider to shunt VINLS and LS/LDO, but not connect those to PMID (if necessary, we could place a 1 µF capacitor from VINLS to GND). Will this work or does VINLS always have to be connected to PMID?
Any help is highly appreciated,
Marc
