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UCC28704: High voltage on teh CS pin

Sunset
Genius 13475 points
Part Number: UCC28704

Hello Team,

As I read in the data sheet, the CS pin is typ. 356mV with constant current regulation.

During a measurement I noticed that the voltage is up to 750mV with constant current regulation, as you can see in the following picture.

 

The voltage at the CS pin is shown in blue.

Yellow = DRV-Pin (MOSFET gate)

Red = Vdd Pin

Green = 24V output voltage

 

 

I am using a circuit as described in the datasheet with the following values:

  • Cdd = 12µF
  • Rs1 = 100k
  • Rs2 = 31k8
  • Rcs = 1R5
  • Rcl = 560R

The output voltage is 24V and the output current is 250mA.

  • Is there an explanation for the higher voltage on the CS pin?

Because of the high current through the current-sense-resistors (and transformer) I have a problem with saturation of the transformer.

Additionally I have a problem with saturation at the startup. The voltage at the current sense pin rises up to over 1 V as you can see in the picture below.

 

The voltage at the CS pin is shown in blue.

Yellow = DRV-Pin (MOSFET gate)

Red = Vdd Pin

Green = 24V output voltage

Thanks,

SunSet

  • 0
    TI__Guru 70445 points

    Hello,

    I am reviewing your inquiry and will get back  to you shortly.

    Regards,

  • +1 in reply to Mike O'
    TI__Guru 70445 points

    Hello,

    At maximum load the CS signal should be around 750 mV.  So that is O.K.

    In regards to the leading edge current spike in the waveform you have I believe is blanked out by the leading edge current blanking circuitry inside the device.

    So I don't think this is an issue either.

    I also do not see a saturated current waveform in your CS signal.  If this was the case the CS signal would be curved even parabolic in nature.

    When it comes to the CS signal.  When you drive the gate of the FET there is a gate to source capacitor on the FET that needs to be charged.  This is causing the leading edge current spike that you are seeing.  This is observed on most CS signals and why controllers generally have leading edge cs blanking to ignore this spike.  In the case of the UCC28704 the leading edge blanking time (TCSLEB) is roughly 255 ns.

    There is a UCC28704 10 W evaluation module that you may want to evaluate to see how the UCC28704 behaves with changes in load, line and large signal transients.  There are waveforms in the User's Guide that show how the device operates as well in a 10 W system.  That is also in the following link as well. 

    https://www.ti.com/lit/pdf/sluubf1

    If this resolved you issue please check resolved at the end of thread.

    Regards,