This design for CPU core1V8. It use 3 phase design and phase shedding option enabled. It is noticed that at initial stage 2 phases are on and at some point, switching frequency start increasing. It is designed for 800Khz but when frequency reach around 1MHz, 3rd phase turns on. But frequency still continue to increase and when it reaches above 2Mhz, Phase 1 and Phase 2 current start falling as shown below , current in phase 3 tries to increase. At this point, output voltage starts increasing and it reach OVP limit and POL shut down.
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