• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 80 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM61460: About PG deglitch time

Albert Sun
Intellectual 330 points
Part Number: LM61460
Other Parts Discussed in Thread: LMR33630,

Hi,

I am confused why 6A LM61460 PG deglitch time is much lower than LMR33630's PG deglitch time? And why LM61460's rising deglitch time is much higher than LMR33630? Any consideration? I do not think it has effect to actual power up or reset. Thanks!

LMR33630 both 60-170us for PG rising and falling

LM61460 Rising 2ms falling 120us

-A

  • 0
    TI__Guru 50120 points

    Hello,

    I don't think this has any impact to power up or reset. The LM61460 has the below PGOOD timing diagram. The T_PGDFLT(rise) is longer just to ensure that the output voltage is regulated and steady for some time. Then the PGOOD flag will pull high to indicate it is in regulation. 

    LM61460-Q1 PGOOD Timing Diagram

    This was something that design wanted to implement in this IC but it doesn't look like this long delay was implemented in the LMR33630. 

    Note that the Power-Good-Timing Behavior for LMR33630 is  when the output voltage has reached 95% of Vout and PG pulls up immediately. 

    Perhaps the question here is whether you want an IC that has PG pull up when VOUT reaches 95% of regulation point, or an IC that has PG pull up when VOUT is regulated to the final Vout point. 

    Regards,

    Jimmy